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We have put some of the quiz
stats here.

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The mean was about 75%.
And I must tell you that that

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is very impressive.
I guess MIT undergrads never

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cease to amaze me.
And this was not an easy quiz.

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This was a relatively hard
quiz.

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And that average implies that
you guys did well on a

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relatively hard quiz.
Good.

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Let's get back to our final
lecture on amplifiers and small

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signal circuits.
And as always let me start with

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a review.
Very quickly --

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-- we came up with a notation
to represent small signals.

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And our notation looked like
this.

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Our total variable was small
and capital, and this was a DC

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bias and this was a small
signal.

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This is also called the
operating point.

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And the small signal is also
called the incremental signal.

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In general, if you have some
function, some variable of

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interest in the circuit,
say a total variable V out,

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let's say it relates to some
input variable as F of VI.

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So mathematically we can find
out V out by simply finding the

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slope of this function at the
operating point and then

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multiplying it by the
incremental change in the input.

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Gold standard math.
So we do the slope of this

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function and evaluate it at the
operating point.

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So this would give us the slope
of the function.

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And multiply that by small VI,
which is incremental change.

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This is standard math.
What this will tell you is

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given a small change in VI this
function gives you,

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this expression gives you the
small change in V out.

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And in lecture we have pretty
much used this method so far,

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used the math to get to where
we wanted it to be.

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And then the way we provided
biasing and so on was for our

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amplifier in particular we had a
bias voltage,

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some small signal value,
VS.

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And this was output which was
also given to be some output

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operating point plus a small
change, which was a change in

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the output voltage.
So what we have done here is

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mathematically computed small V
out.

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And what I am showing you here
is to get the same effect in a

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circuit is you build your
circuit and replace what used to

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be a total variable with a DC
bias plus a small change.

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And then you will get your
output here.

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And this output will relate to
this input using this

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expression.

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So this is more review.
To continue on with the math

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review, for our amplifier VO was
given to be VS-K/2(vI-VT)^2 RL.

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So this was the output versus
input relationship for the

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amplifier.
And mathematically I could get

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the small change in the output
VO by simply differentiating

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this function with respect to
VI, evaluating that function,

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at capital VI and multiplying
by the small change in the

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input.
And the resulting expression

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that we got for small VO --

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-- was simply minus K,
this was our DC value,

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and RL times small VI.
So we derived all of this the

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last time.
So nothing new so far.

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So my small signal output was
some function given by

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K(VI-VT)RL times small vi.
And notice that this is how VI

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relates to VO.
And this is a constant with

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respect to VI.
V capital I is a DC bias,

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so this is a constant.
So therefore this is the linear

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relationship that we had set out
to get.

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This term here,
for reasons we will see today,

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this term here K(VI-VT) is
called gm.

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Transconductance.
We will look at it in more

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detail a little later.

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Even more review.

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So I can draw the transfer
function and plot VO versus VI.

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Another way to graphically view
what is going on is by plotting

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the load line curve for this
circuit, so this is VI.

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And I said we draw that by
first plotting the --

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These were our MOSFET curves.
And we know that at some point

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the MOSFET gets into saturation,
so this curve was iDS=K/2 VO^2.

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And to the right side of the
curve the MOSFET is in

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saturation.
And we said we will adhere to

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the saturation discipline and
operate in this regime.

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When the MOSFET gets into this
region it is in its triode

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region.
And then we could draw the load

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line here.
The load line codified the

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following relationship,
iDS=VS/RL-VO/RL.

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This was a load line.
So I have superimposed a load

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line on the device
characteristics,

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and I am going to show you a
little demonstration based on

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that at this point.
So these curves were drawn for

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increasing values of VI.
And if I choose some operating

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point here then this point would
correspond to some bias,

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this bias point would
correspond to some input voltage

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VI, a corresponding output bias
VO and a corresponding current

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iDS.
So iDS capitals,

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VO capitals,
VI capitals represent the

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operating point values for our
little circuit.

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So far there is nothing new.
One thing we stopped the last

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time by pointing out that the
gain of our amplifier,

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this is the gain,
-K(VI-VT)RL.

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That is the gain A of the
amplifier.

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That gain related to VI.
A gain was proportional to

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VI-VT.
So therefore if I increased VI,

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I would get more gain.
So the question is how do we

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choose a bias point?
And in our particular example,

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let's say we are free to play
around with VI.

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So we play around with VI and I
can choose various bias points.

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So where do you set the bias
point?

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What are the various
characteristics of the circuit

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that relate to my bias point?
Well, first,

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of course, is gain.
The gain depends on how I

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choose VI.
I will show you that in a

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moment.
The second important thing,

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in other words,
if I choose a bias point that

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is a small VI then my gain is
going to be smaller.

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If I choose a bias point that's
at a much higher value of VI,

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I get a bigger gain.
The second important

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consideration is operating
range.

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Notice that if I choose a bias
point here then as the input

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changes --
Notice VI in this graph goes up

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or down, and I would be
traversing and following

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different lines here in my
MOSFET characteristic.

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And as VI increases the
operating point would come up

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here and so on.
So if about this operating

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point I varied my input voltage
VI then, so let's say about this

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operating point,
if my input VI,

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my small signal VI varied about
a small range then

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correspondingly the output value
would vary about this part of my

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load line.
So notice now that the

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operating range,
how far can VI vary before the

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MOSFET goes out of its
saturation discipline?

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Well, on the low side my VI can
come down to here.

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And we looked at the operating
ranges for an amplifier.

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And I can come all the way down
to VT.

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At that point the output will
come here.

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Similarly at the high end VI
could get up to a high value.

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And we computed that value in
the last lecture.

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And the corresponding value of
the input would be here.

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So in some sense I can traverse
all the way from here to here

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and have the MOSFET remain in
saturation.

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Remember we are not talking
about linearity right now,

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just about the valid operating
range based on my definition

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which is that the MOSFET should
stay in saturation.

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So if I chose my operating
point here then I get this range

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here.
And, on the other hand,

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if I chose my operating point
to be here, for negative

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excursions of the input signal I
have a very small amount before

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I hit cutoff.
So if I chose my operating

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point here then for negative
traversals of VI about the

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operating point I very quickly
hit cutoff.

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So if I want symmetric swings
then this is the best that I can

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do in terms of the valid input
operating range if I want

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symmetric swings given that this
is my bias point.

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On the other hand,
if I chose my bias point

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somewhere here,
or very carefully chose my bias

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point then my input can vary on
a much wider region and still

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get symmetric swings.
And so therefore the choice of

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bias point also influences the
maximum swing range of my input

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signal.
I shouldn't call this operating

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range.
I should call it input swing

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range.
We defined the valid input

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operating range as the range for
which the amplifier satisfied

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the saturation discipline.
So the two key issues,

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gain and the input swing.
Let me show you a quick demo

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and try to point out on a graph
some of the characteristics that

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relate to the matter we have
been talking about so far.

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So what I show here are these
curves for the MOSFET.

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This is VO and this iDS.
This is the zero point.

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Ignore this line down here.
This line up here corresponds

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to the output voltage VO.
What I am going to do now is,

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through some careful circuit
hacking, I'm going to show show

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you a load line and show you the
bias point, and show you how the

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bias point can be moved up and
down by changing the input

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voltage which changes the
corresponding output voltage.

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It is hardly visible out there.

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Is it there?
OK.

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It is not really clear,
but notice that as I increase

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my input, I am increasing my
input.

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My output keeps coming down.
And I hope your eyesight is

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better than mine because I don't
see a dot up there.

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I am amazed.
This is the first time this has

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happened to me.
That's OK.

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All right.
As you can see,

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as I change the input value the
output operating point changes,

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and the dot out there
traverses, articulates a load

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line.
I guess I have to believe that

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there is a dot out there.
Next what I will do is show you

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some more fun stuff.
What I will do is instead of

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having just a dot by having a DC
voltage, let me apply an input

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sinusoid.
So if I apply an input sinusoid

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at some bias then I should see
an articulation of the

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corresponding region of the load
line corresponding to the input.

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So, as you can see here,
now the bottom line,

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here is my input and this is my
output.

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And notice that this the region
of the load line articulated

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when the input is of this
magnitude.

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Now let's have some fun.
As I increase my input,

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you can see that a larger
portion of the load line is

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articulated, right?
There you go.

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And as I decrease my input a
smaller region of the load line

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is articulated.
Let's leave it here for a

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moment.
And what I will do next,

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this is the region here that we
are looking at,

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let me increase the bias.
If I increase the bias,

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if I increase VI,
what do you think should happen

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to this line here?
Well, if I increase the bias,

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the line should go up,
right?

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00:17:06,000 --> 00:17:09,000
Because remember the dot?
The dot is in the middle of

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this thing here.
If I increase the bias this

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00:17:12,000 --> 00:17:15,000
should move up here.
So that line moves up.

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Do you expect anything else to
happen to that line?

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Pardon?
It increases,

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00:17:20,000 --> 00:17:23,000
exactly.
If I increase the bias point to

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00:17:23,000 --> 00:17:26,000
here then this must also
increase because my gain has

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increased.
Let me do that.

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So let me increase the input
bias.

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Indeed notice that the region
of the load line articulated is

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larger now.
Let me decrease the bias.

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00:17:41,000 --> 00:17:46,000
And notice that because the
gain is smaller the little

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segment shown is also smaller.
I have shown you two things so

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00:17:51,000 --> 00:17:54,000
far.
One is that I as I increase my

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bias the line indeed rises up
corresponding to a higher value

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for the input operating point.
And the second is that I get a

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00:18:06,000 --> 00:18:11,000
larger swing in the output as I
increase the bias.

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Just to show that for those
like me who were visually

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challenged in terms of viewing
that little dot up there,

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00:18:21,000 --> 00:18:26,000
let me get some audio so you
can actually hear the sinusoidal

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tone.
It is a big annoying.

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As I reduce the bias the gain
is decreased.

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As I increase the bias you can
see that the gain is increased

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and the tone is louder.
Let's have some more fun and

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let's play some music now.
And what I am going to show you

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with the music --
The reason I play the music is

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not just for fun.
Well, it's 85% fun and 15%

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learning.
Can we turn it on for a second?

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What I would like to do is,
as we play the music,

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00:19:12,000 --> 00:19:17,000
the reason I am playing the
music for that 15% is so you can

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listen to distortion.
I want you to listen to the

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distortion.
That is when the articulation

234
00:19:24,000 --> 00:19:30,000
is here you are not going to get
much distortion.

235
00:19:30,000 --> 00:19:34,000
But as I get into cutoff you
should be getting a bunch of

236
00:19:34,000 --> 00:19:37,000
distortion.
Similarly, as you get into the

237
00:19:37,000 --> 00:19:42,000
triode region you should also be
getting distortion because the

238
00:19:42,000 --> 00:19:47,000
amplification from being
somewhat nonlinear here becomes

239
00:19:47,000 --> 00:19:50,000
highly nonlinear at those two
points.

240
00:19:50,000 --> 00:19:54,000
So let's just play the signal.
So volume increases,

241
00:19:54,000 --> 00:19:58,000
or rather the amplitude
increases by increasing the

242
00:19:58,000 --> 00:20:02,000
bias.
Now you should hear the volume

243
00:20:02,000 --> 00:20:05,000
go down and distortion.

244
00:20:15,000 --> 00:20:17,000
So notice now that the bias
point is way down here.

245
00:20:17,000 --> 00:20:20,000
So the gain is very low,
and plus there is a distortion

246
00:20:20,000 --> 00:20:23,000
because of cutoff.
Now what I will do is blast it

247
00:20:23,000 --> 00:20:26,000
up here, and you will see that
the volume has gone up but then

248
00:20:26,000 --> 00:20:29,000
you see distortion again.
Let's see if you can stand the

249
00:20:29,000 --> 00:20:31,000
volume here.

250
00:20:54,000 --> 00:20:56,000
Even the CD doesn't like that.

251
00:21:02,000 --> 00:21:05,000
Notice that as I went up here
the volume kept increasing

252
00:21:05,000 --> 00:21:09,000
because the gain kept
increasing, but as I got into

253
00:21:09,000 --> 00:21:12,000
the triode region I began to
lose my gain because,

254
00:21:12,000 --> 00:21:17,000
remember, the amplifier doesn't
have gain in the triode region,

255
00:21:17,000 --> 00:21:21,000
MOSFET in its triode region,
and we also get a bunch of

256
00:21:21,000 --> 00:21:24,000
distortion out there.
Finally, it turns out that as

257
00:21:24,000 --> 00:21:28,000
people are building amplifiers
--

258
00:21:28,000 --> 00:21:33,000
I think this was in the mid to
late `50s and `60s and so on.

259
00:21:33,000 --> 00:21:38,000
They said man,
electrical engineers are not

260
00:21:38,000 --> 00:21:44,000
going to get their thing right.
So they invented a new kind of

261
00:21:44,000 --> 00:21:48,000
music which was much more
tolerant to distortion.

262
00:21:48,000 --> 00:21:52,000
And I will play that music for
you.

263
00:21:52,000 --> 00:21:57,000
It is called hard rock.
I challenge you to tell me it

264
00:21:57,000 --> 00:22:00,000
is distorting.

265
00:22:20,000 --> 00:22:22,000
Sounds good to me.

266
00:22:30,000 --> 00:22:31,000
OK.
All right.

267
00:22:31,000 --> 00:22:34,000
That'll do it.
Thank you.

268
00:22:34,000 --> 00:22:40,000
I hope there are no hard rock
musicians in here who will come

269
00:22:40,000 --> 00:22:45,000
and beat me up after lecture or
something.

270
00:22:45,000 --> 00:22:49,000
All right.
Believe it or not most of that

271
00:22:49,000 --> 00:22:53,000
was review.
There is nothing new today

272
00:22:53,000 --> 00:22:59,000
besides some fun and games and
so on.

273
00:22:59,000 --> 00:23:03,000
I will give you a breather for
five seconds before jumping into

274
00:23:03,000 --> 00:23:05,000
something even more fun.

275
00:23:27,000 --> 00:23:30,000
I want you to look at the
middle board here.

276
00:23:30,000 --> 00:23:33,000
And, as I told you in the
beginning of 6.002,

277
00:23:33,000 --> 00:23:36,000
engineering is about building
useful systems.

278
00:23:36,000 --> 00:23:40,000
Engineering is not about
showing off at math or saying

279
00:23:40,000 --> 00:23:43,000
man, I am really cool in math
and stuff.

280
00:23:43,000 --> 00:23:46,000
Engineering is about building
useful systems,

281
00:23:46,000 --> 00:23:49,000
and you want to find the
simplest, easiest,

282
00:23:49,000 --> 00:23:53,000
cheapest way to get there.
Unlike deep areas of math and

283
00:23:53,000 --> 00:23:55,000
theory and so on,
the beauty is in the

284
00:23:55,000 --> 00:23:59,000
simplicity.
So the aesthetics are in how

285
00:23:59,000 --> 00:24:02,000
simply can we make things and
still get to where we want to

286
00:24:02,000 --> 00:24:04,000
be?
All through the course what you

287
00:24:04,000 --> 00:24:08,000
will be seeing happening again
and again and again is when

288
00:24:08,000 --> 00:24:11,000
things begin to get too grovelly
in terms of math,

289
00:24:11,000 --> 00:24:14,000
we will step back and say oops,
we are engineers,

290
00:24:14,000 --> 00:24:16,000
remember?
Let's find a much simpler way

291
00:24:16,000 --> 00:24:19,000
to do it and use intuition.
So time and time and time

292
00:24:19,000 --> 00:24:23,000
again, I am going to take you on
a simpler path where you can

293
00:24:23,000 --> 00:24:25,000
solve things by inspection by
pure intuition.

294
00:24:25,000 --> 00:24:30,000
Most circuit designers do that.
So take a look at this.

295
00:24:30,000 --> 00:24:33,000
I don't like this nasty
differentiation here.

296
00:24:33,000 --> 00:24:37,000
That's getting into late high
school calculus and so on.

297
00:24:37,000 --> 00:24:42,000
Let's avoid the math and let's
see if you find some way of

298
00:24:42,000 --> 00:24:45,000
doing it that is even much more
simpler.

299
00:24:45,000 --> 00:24:50,000
And that is what I will do next
and show you what is called the

300
00:24:50,000 --> 00:24:54,000
small signal circuit view.
A purely circuit way of

301
00:24:54,000 --> 00:24:58,000
developing the small signal
model.

302
00:24:58,000 --> 00:25:02,000
So let me just start by drawing
the large signal equivalent

303
00:25:02,000 --> 00:25:06,000
circuit for you.
I will draw it here for reasons

304
00:25:06,000 --> 00:25:10,000
that will be obvious at the end
of the class.

305
00:25:45,000 --> 00:25:48,000
All right.
This is the large signal

306
00:25:48,000 --> 00:25:54,000
equivalent circuit model for our
MOSFET amplifier.

307
00:25:54,000 --> 00:25:59,000
VS and here is my current
source.

308
00:25:59,000 --> 00:26:02,000
iDS relates to the square of VI
minus VT.

309
00:26:02,000 --> 00:26:06,000
So stare at that for a second.
And that is a nonlinear

310
00:26:06,000 --> 00:26:10,000
circuit.
iDS relates to the square of VI

311
00:26:10,000 --> 00:26:13,000
minus VT.
Let me start by making the

312
00:26:13,000 --> 00:26:17,000
following claim.
Let me shoot from the hip here

313
00:26:17,000 --> 00:26:22,000
and make the following grand
claim, and then I will show you

314
00:26:22,000 --> 00:26:26,000
how I can prove that claim.
The grand claim I am about to

315
00:26:26,000 --> 00:26:32,000
make says the following.
A bunch of little devices here.

316
00:26:32,000 --> 00:26:37,000
It is a nonlinear circuit.
Just suppose for a moment we do

317
00:26:37,000 --> 00:26:41,000
a Gedanken experiment.
Suppose I replace each of my

318
00:26:41,000 --> 00:26:46,000
circuit elements here with its
linearized element equivalent.

319
00:26:46,000 --> 00:26:49,000
In other words,
here is a VS source,

320
00:26:49,000 --> 00:26:54,000
here is a dependent current
source, let me replace them with

321
00:26:54,000 --> 00:26:59,000
their linear equivalent circuit
models.

322
00:26:59,000 --> 00:27:02,000
In other words,
with their corresponding small

323
00:27:02,000 --> 00:27:05,000
signal element models.
And I will show you what those

324
00:27:05,000 --> 00:27:08,000
are in a second.
The resistor has a

325
00:27:08,000 --> 00:27:10,000
corresponding small signal
element.

326
00:27:10,000 --> 00:27:15,000
The dependent current source
has a corresponding small signal

327
00:27:15,000 --> 00:27:18,000
behavioral element model.
And what I am going to do is

328
00:27:18,000 --> 00:27:22,000
keep the same circuit
connections and simply pull out

329
00:27:22,000 --> 00:27:26,000
the large signal model for the
element and replace it with a

330
00:27:26,000 --> 00:27:31,000
small signal element model.
And by the nature of the small

331
00:27:31,000 --> 00:27:34,000
signal model they are all going
to be linear.

332
00:27:34,000 --> 00:27:37,000
So what I am going to be left
with is a linear circuit with

333
00:27:37,000 --> 00:27:39,000
simple linear circuit elements
in there.

334
00:27:39,000 --> 00:27:42,000
And then once I have a linear
circuit, I should be able to

335
00:27:42,000 --> 00:27:45,000
analyze that linear circuit
using methods 1,

336
00:27:45,000 --> 00:27:48,000
2 and 3, superposition,
Thevenin, node method and so

337
00:27:48,000 --> 00:27:50,000
on.
And certainly the intuitive

338
00:27:50,000 --> 00:27:53,000
methods like superposition and
Thevenin, which make life a lot

339
00:27:53,000 --> 00:27:56,000
easier for me with linear
models, and thereby get the

340
00:27:56,000 --> 00:28:00,000
function that I am looking for
very quickly.

341
00:28:00,000 --> 00:28:04,000
Again, my claim is that I can
replace each of these large

342
00:28:04,000 --> 00:28:09,000
signal models by just small
signal equivalents and then just

343
00:28:09,000 --> 00:28:14,000
analyze the resultant circuit.
And I claim that I should be

344
00:28:14,000 --> 00:28:18,000
able to get the same answer.
That's a claim.

345
00:28:18,000 --> 00:28:21,000
All right?
So what I will do is give you

346
00:28:21,000 --> 00:28:24,000
an informal proof for why I can
do that.

347
00:28:24,000 --> 00:28:29,000
And I also ask you to refer to
Section 8.2.1 of the course

348
00:28:29,000 --> 00:28:33,000
notes to go through the
foundations of the small circuit

349
00:28:33,000 --> 00:28:39,000
model in more detail.
The intuition is that,

350
00:28:39,000 --> 00:28:43,000
remember KVL and KCL?
I can write down KVL and KCL

351
00:28:43,000 --> 00:28:49,000
for every loop in that circuit
and every node in that circuit.

352
00:28:49,000 --> 00:28:53,000
If I do KVL and KCL,
I will end up with something

353
00:28:53,000 --> 00:28:57,000
like this.
For the input loop I get VI

354
00:28:57,000 --> 00:29:00,000
something or the other applying
KVL.

355
00:29:00,000 --> 00:29:07,000
For the output loop I get V out
something or the other.

356
00:29:07,000 --> 00:29:11,000
And then applying KCL I get
some other equation in iDS.

357
00:29:11,000 --> 00:29:16,000
So here are my KVL and KCL
equations for that circuit.

358
00:29:16,000 --> 00:29:22,000
Now, KVL and KCL are simply a
different representation of the

359
00:29:22,000 --> 00:29:27,000
circuit because within those KVL
and KCL is encoded the topology

360
00:29:27,000 --> 00:29:32,000
of the circuit.
Remember each KVL equation

361
00:29:32,000 --> 00:29:36,000
represents a loop and each KCL
equation represents how nodes

362
00:29:36,000 --> 00:29:41,000
are connected together.
So KVL and KCL equations encode

363
00:29:41,000 --> 00:29:44,000
within them the topology of my
circuit.

364
00:29:44,000 --> 00:29:47,000
What I do next is,
say, I replace each of these

365
00:29:47,000 --> 00:29:52,000
with the bias plus the small
signal, so I get the bias plus

366
00:29:52,000 --> 00:29:57,000
the small signal and keep the
equations the same.

367
00:30:10,000 --> 00:30:14,000
All I have done in my big set
of KVL, KCL equations,

368
00:30:14,000 --> 00:30:18,000
I have simply replaced the
total variable with the large

369
00:30:18,000 --> 00:30:21,000
signal variable and the small
signal quantity.

370
00:30:21,000 --> 00:30:26,000
Then comes a key trick.
The key trick is that because

371
00:30:26,000 --> 00:30:30,000
the bias point variables,
they are a valid solution to

372
00:30:30,000 --> 00:30:33,000
the circuit.
The circuit is in this

373
00:30:33,000 --> 00:30:36,000
quiescent state,
and those are valid solutions

374
00:30:36,000 --> 00:30:39,000
to circuit.
So therefore I can cancel them

375
00:30:39,000 --> 00:30:42,000
out.
So the VI, the large signal

376
00:30:42,000 --> 00:30:45,000
values can be cancelled out
leaving just small signal

377
00:30:45,000 --> 00:30:48,000
variables in there.
So from the KVL,

378
00:30:48,000 --> 00:30:52,000
KCL equations I can cancel out
the large signal values,

379
00:30:52,000 --> 00:30:56,000
the DC bias points because they
satisfy the KVL and KCL

380
00:30:56,000 --> 00:30:59,000
themselves.
In other words,

381
00:30:59,000 --> 00:31:02,000
I could have written VI plus V
out and so on.

382
00:31:02,000 --> 00:31:07,000
Since they are satisfied I just
strike out the large signal

383
00:31:07,000 --> 00:31:11,000
variable from both sides of each
of these equations,

384
00:31:11,000 --> 00:31:16,000
so what is left is the same
KVL, KCL equations but with

385
00:31:16,000 --> 00:31:20,000
small variables in place of the
big variables.

386
00:31:20,000 --> 00:31:24,000
What that should tell you,
this informal proof should tell

387
00:31:24,000 --> 00:31:29,000
you is that the small signal
variables should then satisfy

388
00:31:29,000 --> 00:31:34,000
the same form of the KVL,
KCL equations that the total

389
00:31:34,000 --> 00:31:38,000
variables satisfy.
And because the KVL,

390
00:31:38,000 --> 00:31:43,000
KCL equations are a reflection
of the topology of the circuit,

391
00:31:43,000 --> 00:31:48,000
what that says is that the
small signal variables must also

392
00:31:48,000 --> 00:31:52,000
satisfy KVL and KCL.
And since these arrive from the

393
00:31:52,000 --> 00:31:56,000
small signal elements that says
that I can replace the big

394
00:31:56,000 --> 00:32:01,000
elements with the small elements
and KVL and KCL will hold for

395
00:32:01,000 --> 00:32:06,000
the resulting circuit.
This is a very quick breeze

396
00:32:06,000 --> 00:32:11,000
through, an informal proof to
show that I can replace the big

397
00:32:11,000 --> 00:32:17,000
elements with the corresponding
little element models and then

398
00:32:17,000 --> 00:32:22,000
simply apply linear techniques.
Refer to Section 8.2.1 for more

399
00:32:22,000 --> 00:32:28,000
foundations and more discussion
about the foundations for why we

400
00:32:28,000 --> 00:32:34,000
can do this.
That brings up the small signal

401
00:32:34,000 --> 00:32:40,000
circuit method.
The circuit method for small

402
00:32:40,000 --> 00:32:47,000
signal analysis has three steps.
The first step is find

403
00:32:47,000 --> 00:32:55,000
operating point by using LS.
First you analyze your large

404
00:32:55,000 --> 00:33:02,000
signal circuit and find the
operating point.

405
00:33:02,000 --> 00:33:06,000
You have to do this,
because remember,

406
00:33:06,000 --> 00:33:14,000
the small signal models depend
on the operating point values.

407
00:33:14,000 --> 00:33:21,000
Remember the gain of our
amplifier depended on the bias

408
00:33:21,000 --> 00:33:25,000
point.
Second step is develop small

409
00:33:25,000 --> 00:33:34,000
signal models of elements.
Second step is take each of the

410
00:33:34,000 --> 00:33:41,000
elements in your circuit and
find their equivalent small

411
00:33:41,000 --> 00:33:46,000
circuit model for each of the
elements.

412
00:33:46,000 --> 00:33:55,000
Third step is replace original
elements with their small signal

413
00:33:55,000 --> 00:34:01,000
model elements.
Third step is simply take the

414
00:34:01,000 --> 00:34:08,000
large elements and replace them
with their small signal

415
00:34:08,000 --> 00:34:14,000
equivalent models.
Then analyze resulting circuit,

416
00:34:14,000 --> 00:34:19,000
and that circuit will be a
linear circuit.

417
00:34:19,000 --> 00:34:26,000
So let's do an example.
I will just use the amplifier

418
00:34:26,000 --> 00:34:34,000
as an example of this method.
And convince you that you are

419
00:34:34,000 --> 00:34:40,000
going to get the same expression
at the end, but just so,

420
00:34:40,000 --> 00:34:46,000
so simply without even the
smallest amount of grubby math.

421
00:34:46,000 --> 00:34:51,000
Three steps.
The first step is to find the

422
00:34:51,000 --> 00:34:56,000
operating point using the large
signal model.

423
00:34:56,000 --> 00:35:01,000
And let me just do that here.
I get my V out =

424
00:35:01,000 --> 00:35:07,000
VS-K/2(VI-VT)^2 RL.
Let me just write down that out

425
00:35:07,000 --> 00:35:09,000
here.
Don't worry about copying that

426
00:35:09,000 --> 00:35:12,000
down.
It is on the last page of your

427
00:35:12,000 --> 00:35:15,000
notes.
The first step of the method

428
00:35:15,000 --> 00:35:19,000
simply applies the large signal
model and finds out the behavior

429
00:35:19,000 --> 00:35:24,000
of that circuit to find out what
the bias point values are.

430
00:35:24,000 --> 00:35:28,000
The second step is to develop
the small signal model of my

431
00:35:28,000 --> 00:35:33,000
elements.
How do I go about developing

432
00:35:33,000 --> 00:35:36,000
the small signal models of
elements?

433
00:35:36,000 --> 00:35:42,000
Let's start with the MOSFET.
The large signal model for the

434
00:35:42,000 --> 00:35:46,000
MOSFET looks like this.

435
00:35:53,000 --> 00:35:56,000
Here is my Vgs.
This is my gate.

436
00:35:56,000 --> 00:36:00,000
This is my drain.
This is my source.

437
00:36:00,000 --> 00:36:03,000
And I know my iDS to be
K/2(Vgs-VT)^2.

438
00:36:03,000 --> 00:36:07,000
So this is the large signal
model for the MOSFET,

439
00:36:07,000 --> 00:36:12,000
again in saturation.
I am talking about all of these

440
00:36:12,000 --> 00:36:15,000
models are under the saturation
discipline.

441
00:36:15,000 --> 00:36:20,000
So Vgs relates to iDS in the
following way for the MOSFET.

442
00:36:20,000 --> 00:36:24,000
That is iDS,
is K/2 and that is my square

443
00:36:24,000 --> 00:36:28,000
law relationship.
So what is a corresponding

444
00:36:28,000 --> 00:36:34,000
small signal model?
I go ahead and start with this.

445
00:36:34,000 --> 00:36:40,000
The corresponding small signal
model simply says that iDS

446
00:36:40,000 --> 00:36:43,000
relates to Vgs in the following
way.

447
00:36:43,000 --> 00:36:49,000
All I have to do is find a
small signal equivalent where I

448
00:36:49,000 --> 00:36:54,000
need to find out,
given a small change in the

449
00:36:54,000 --> 00:37:00,000
input Vgs, what is the small
change in the iDS?

450
00:37:00,000 --> 00:37:04,000
So I can apply my standard
trick to a much simpler

451
00:37:04,000 --> 00:37:08,000
expression here,
which is iDS simply,

452
00:37:08,000 --> 00:37:14,000
I differentiate this function
with respect to Vgs.

453
00:37:19,000 --> 00:37:24,000
So I don't completely eliminate
the math here,

454
00:37:24,000 --> 00:37:28,000
but it is a much simpler
problem here.

455
00:37:28,000 --> 00:37:34,000
At Vgs equals the bias point
times small vgs.

456
00:37:34,000 --> 00:37:41,000
I can find the small change in
iDS corresponding to a small

457
00:37:41,000 --> 00:37:47,000
change in the input using this
expression.

458
00:37:47,000 --> 00:37:52,000
That gives me iDS as simply
K(Vgs-VT) vgs.

459
00:37:52,000 --> 00:37:58,000
I call this gm,
and I will tell you why in a

460
00:37:58,000 --> 00:38:02,000
second.
So what does this expression

461
00:38:02,000 --> 00:38:05,000
say?
This expression says that if I

462
00:38:05,000 --> 00:38:10,000
have a small change in Vgs then
this will be my small change in

463
00:38:10,000 --> 00:38:12,000
iDS.
Notice that the resulting small

464
00:38:12,000 --> 00:38:16,000
signal model is also a dependent
current source.

465
00:38:16,000 --> 00:38:20,000
It is a voltage controlled
dependent current source.

466
00:38:20,000 --> 00:38:25,000
So the output is the current,
and it is a dependent current

467
00:38:25,000 --> 00:38:30,000
source and it depends on the
input voltage.

468
00:38:30,000 --> 00:38:33,000
The good news is that notice
that this one,

469
00:38:33,000 --> 00:38:39,000
this expression here gm is a
constant related to the bias

470
00:38:39,000 --> 00:38:42,000
point values.
Therefore, notice that the

471
00:38:42,000 --> 00:38:47,000
small signal model for the
MOSFET in saturation,

472
00:38:47,000 --> 00:38:51,000
not surprisingly,
is a linear voltage controlled

473
00:38:51,000 --> 00:38:56,000
current source according to the
following expression.

474
00:38:56,000 --> 00:39:01,000
So iDS=gm Vgs.
Gm is a representation for

475
00:39:01,000 --> 00:39:05,000
K(Vgs-VT) and is called a
transconductance.

476
00:39:05,000 --> 00:39:10,000
It is called a transconductance
because it, in some sense,

477
00:39:10,000 --> 00:39:15,000
deflects the conductance
properties of this based on the

478
00:39:15,000 --> 00:39:19,000
input.
So it is a transconductance.

479
00:39:19,000 --> 00:39:24,000
So this value is called Vgs.
Therefore, I can build the

480
00:39:24,000 --> 00:39:32,000
small signal model as follows.
Vgs is a voltage controlled

481
00:39:32,000 --> 00:39:38,000
current source and iDS is simply
gm Vgs.

482
00:39:38,000 --> 00:39:45,000
So this is my gate,
drain, source.

483
00:39:55,000 --> 00:39:59,000
So that is the small signal
model for my MOSFET.

484
00:39:59,000 --> 00:40:05,000
As a next step what are the
other elements in my circuit?

485
00:40:05,000 --> 00:40:08,000
Let's see.
I have a voltage source and I

486
00:40:08,000 --> 00:40:12,000
have a resistor,
so let me find out the

487
00:40:12,000 --> 00:40:17,000
corresponding small signal model
for a DC supply VS.

488
00:40:17,000 --> 00:40:21,000
This is Page 7.
I will do it mathematically for

489
00:40:21,000 --> 00:40:27,000
you, but often times it is
always good to do a sanity check

490
00:40:27,000 --> 00:40:31,000
using intuition.
Let me ask you,

491
00:40:31,000 --> 00:40:38,000
the large signal for a DC
supply looks like this.

492
00:40:44,000 --> 00:40:49,000
The element law for a voltage
source is VS equals some capital

493
00:40:49,000 --> 00:40:52,000
VS.
It is a constant voltage.

494
00:40:52,000 --> 00:40:58,000
So what do you expect to be the
small signal model for a voltage

495
00:40:58,000 --> 00:41:01,000
source?
In other words,

496
00:41:01,000 --> 00:41:05,000
for a small change,
suppose I have a small change

497
00:41:05,000 --> 00:41:09,000
in the current,
by how much should the output

498
00:41:09,000 --> 00:41:12,000
VS change?
It shouldn't change.

499
00:41:12,000 --> 00:41:16,000
It is a voltage source.
So what does intuition tell you

500
00:41:16,000 --> 00:41:20,000
is a small signal model for the
voltage source?

501
00:41:20,000 --> 00:41:23,000
A short.
So the key here is that a

502
00:41:23,000 --> 00:41:28,000
voltage source behaves like a
short circuit for small

503
00:41:28,000 --> 00:41:32,000
perturbations.
In other words,

504
00:41:32,000 --> 00:41:38,000
if I change the current flowing
through it by a small amount

505
00:41:38,000 --> 00:41:42,000
somehow, the output is still
going to held at VS.

506
00:41:42,000 --> 00:41:47,000
In other words,
small signals are simply going

507
00:41:47,000 --> 00:41:52,000
to scoot through this voltage
source without having any impact

508
00:41:52,000 --> 00:41:58,000
whatsoever on the voltage.
Or mathematically I could also

509
00:41:58,000 --> 00:42:04,000
do small vs is del by del IS of
VS evaluated at IS equals some

510
00:42:04,000 --> 00:42:10,000
capital IS times small IS.
And therefore VS equals zero.

511
00:42:10,000 --> 00:42:15,000
What that means is that the
small signal model for my

512
00:42:15,000 --> 00:42:20,000
voltage source is simply a short
circuit.

513
00:42:26,000 --> 00:42:31,000
So in a small circuit voltage
sources appear like a short

514
00:42:31,000 --> 00:42:37,000
circuit.
Finally, I have a resistor,

515
00:42:37,000 --> 00:42:42,000
my resistor R.
Let me find out its

516
00:42:42,000 --> 00:42:47,000
corresponding small signal
model.

517
00:42:47,000 --> 00:42:54,000
The large signal model looks
like this R, VR,

518
00:42:54,000 --> 00:42:58,000
IR.
And I know that VR is simply

519
00:42:58,000 --> 00:43:04,000
RIR.
And to find the small signal

520
00:43:04,000 --> 00:43:09,000
equivalent I do del of IRR
divided by del IR for IR

521
00:43:09,000 --> 00:43:14,000
calculated at some constant
value times small IR.

522
00:43:14,000 --> 00:43:21,000
What I am looking to do is to
find out what is the change in

523
00:43:21,000 --> 00:43:29,000
the voltage across R for a small
perturbation in the current?

524
00:43:29,000 --> 00:43:33,000
Again, let me exhort you to
rely on intuition to at least

525
00:43:33,000 --> 00:43:36,000
sanity check your answers.
So what do you think this

526
00:43:36,000 --> 00:43:39,000
should look like?
It's a resistor and I have a

527
00:43:39,000 --> 00:43:43,000
small change in the current,
by what do you expect the

528
00:43:43,000 --> 00:43:45,000
voltage to change?
Think about,

529
00:43:45,000 --> 00:43:49,000
for the next five seconds,
what the small signal model for

530
00:43:49,000 --> 00:43:54,000
this should look like and then I
will go ahead and write down the

531
00:43:54,000 --> 00:43:56,000
answer.

532
00:44:06,000 --> 00:44:09,000
So differentiating I simply get
RIR.

533
00:44:09,000 --> 00:44:15,000
In other words,
for a resistor the small signal

534
00:44:15,000 --> 00:44:19,000
model is the resistor itself.

535
00:44:29,000 --> 00:44:33,000
So what I have done so far,
let me just take you through

536
00:44:33,000 --> 00:44:37,000
where we are right now,
give you the big picture there.

537
00:44:37,000 --> 00:44:41,000
I began by suggesting that
looking to find an even simpler

538
00:44:41,000 --> 00:44:46,000
way to do small signal analysis.
I gave you an informal proof to

539
00:44:46,000 --> 00:44:50,000
show that if I had small signal
element models for all of my

540
00:44:50,000 --> 00:44:55,000
elements, I could simply replace
them in the circuit and then do

541
00:44:55,000 --> 00:44:59,000
a corresponding linear circuit
analysis phase to get the result

542
00:44:59,000 --> 00:45:04,000
I am looking for.
There are three steps to the

543
00:45:04,000 --> 00:45:06,000
method.
As a first step we began by

544
00:45:06,000 --> 00:45:10,000
finding small signal models for
each of our elements.

545
00:45:10,000 --> 00:45:14,000
For the nonlinear MOSFET the
small signal model was a linear

546
00:45:14,000 --> 00:45:18,000
dependent current source.
For a voltage source the

547
00:45:18,000 --> 00:45:21,000
corresponding small signal model
was a short circuit.

548
00:45:21,000 --> 00:45:25,000
Again, that makes sense
intuitively if I change the

549
00:45:25,000 --> 00:45:30,000
current through a voltage source
by a small amount.

550
00:45:30,000 --> 00:45:32,000
By how much does the voltage
change?

551
00:45:32,000 --> 00:45:34,000
It is a voltage source,
silly.

552
00:45:34,000 --> 00:45:38,000
The voltage doesn't change.
So the small signal V,

553
00:45:38,000 --> 00:45:43,000
the small change in the voltage
is zero, and that is the same

554
00:45:43,000 --> 00:45:47,000
thing as a short circuit.
For a resistor by how much does

555
00:45:47,000 --> 00:45:51,000
the voltage change if I change
the current by a small amount?

556
00:45:51,000 --> 00:45:55,000
Well, it will change by R times
the current change,

557
00:45:55,000 --> 00:46:00,000
and that is the property of a
resistor, R.

558
00:46:00,000 --> 00:46:04,000
As a final step what I would
like to do, on Page 8,

559
00:46:04,000 --> 00:46:10,000
I'd like to very quickly draw
for you the small signal circuit

560
00:46:10,000 --> 00:46:14,000
and then analyze it.
This is the large signal

561
00:46:14,000 --> 00:46:18,000
circuit.
That is a large signal circuit.

562
00:46:18,000 --> 00:46:22,000
And let me draw the small
signal circuit.

563
00:46:22,000 --> 00:46:27,000
And the method says simply
pluck out, gouge out each of

564
00:46:27,000 --> 00:46:32,000
these elements.
And simply replace each of

565
00:46:32,000 --> 00:46:37,000
these nasty nonlinear elements
with the corresponding small

566
00:46:37,000 --> 00:46:41,000
signal linear equivalents.
So let's do that.

567
00:46:41,000 --> 00:46:47,000
Remember, for the input you
replace input with its small

568
00:46:47,000 --> 00:46:52,000
signal voltage because I am
telling you that it's sourcing a

569
00:46:52,000 --> 00:46:55,000
small change in VI.
So that is VI.

570
00:46:55,000 --> 00:47:00,000
And then I replace a short for
VS.

571
00:47:00,000 --> 00:47:10,000
I replace an R for RL because
it is an RL itself for the small

572
00:47:10,000 --> 00:47:17,000
signal model.
And then for the dependent

573
00:47:17,000 --> 00:47:27,000
source, we discovered that the
dependent source was a linear

574
00:47:27,000 --> 00:47:35,000
dependent source given where
ids=gmvi.

575
00:47:35,000 --> 00:47:38,000
Remember, this was my small VO.
Here you go.

576
00:47:38,000 --> 00:47:43,000
I have a small signal circuit
here where I have simply created

577
00:47:43,000 --> 00:47:48,000
that by replacing each of the
big elements by little

578
00:47:48,000 --> 00:47:51,000
rinky-dink elements.
Now these are all linear

579
00:47:51,000 --> 00:47:56,000
elements so I can do a really
simple linear analysis.

580
00:47:56,000 --> 00:48:01,000
What method shall we use?
Well, this is so simple.

581
00:48:01,000 --> 00:48:06,000
I will just go ahead and use
the node method.

582
00:48:06,000 --> 00:48:11,000
So applying the node method at
the node with voltage VO,

583
00:48:11,000 --> 00:48:17,000
what I will do is the current
going up, VO divided by RL

584
00:48:17,000 --> 00:48:20,000
equals the current going down
iDS.

585
00:48:20,000 --> 00:48:27,000
And so the current going up is
VO divided by RL and the current

586
00:48:27,000 --> 00:48:33,000
going down is --
Oops, I should have done this.

587
00:48:33,000 --> 00:48:41,000
The total current going out is
zero, so the sum of these two is

588
00:48:41,000 --> 00:48:45,000
zero.
That is my good old node method

589
00:48:45,000 --> 00:48:49,000
here.
And I know that iDS is simply

590
00:48:49,000 --> 00:48:54,000
gmvi equals zero.
So right there I have the

591
00:48:54,000 --> 00:49:03,000
relationship between VO and VI.
So VO is simply minus gmviRL.

592
00:49:03,000 --> 00:49:11,000
And remember gm was simply K VI
minus VT.

593
00:49:17,000 --> 00:49:18,000
We are done,
OK?

594
00:49:18,000 --> 00:49:21,000
What have we here?
I created a linear circuit

595
00:49:21,000 --> 00:49:25,000
which simply comprised small
signal models for each of my big

596
00:49:25,000 --> 00:49:28,000
elements.
And then I simply did a

597
00:49:28,000 --> 00:49:32,000
straightforward linear analysis
using any one of the linear

598
00:49:32,000 --> 00:49:36,000
techniques I knew about.
This is simple enough so I

599
00:49:36,000 --> 00:49:40,000
apply the node method.
And I've got the equation at

600
00:49:40,000 --> 00:49:44,000
this node, simplified it and I
directly got the answer.

601
00:49:44,000 --> 00:49:48,000
In one or two steps I directly
gave you the output as a

602
00:49:48,000 --> 00:49:52,000
function of the input.
It can't get any simpler.

603
00:49:52,000 --> 00:49:55,000
Thank you.