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I will be replacing Professor
Agarwal today because he is

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00:00:11,000 --> 00:00:14,000
away.
I am one of the recitation

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00:00:14,000 --> 00:00:20,000
instructors for those of you who
have not seen me.

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We will talk today about a neat
application of RC networks and

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00:00:27,000 --> 00:00:34,000
expand those to application in
MOS memory systems.

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To connect with everything,
we will get back to the basic

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circuit that we have been
discussing so far.

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And you recall the circuit that
we have been studying,

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the canonical RC with an input
voltage function of t.

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And we had specified that we
solved this problem for the case

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of a step input or a condition
in which a t=0.

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At t greater or equal to zero
vI is equal to some capital VI

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value that for now on is
constant.

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And the other condition that we
discussed was the value of the

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voltage on the capacitor that
would exist at time t=0.

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Let's call that vc(0).
And in general there is some

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finite value here.
It can be zero or it can be

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different from zero.
Given that, we learned how to

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write down directly,
without messing around with

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differential equations,
the answer for the voltage on

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the capacitor vc(t),
let me define also my vc right

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here, is equal to VI,
the final value,

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plus vc(0), the initial value
on the capacitor,

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minus the final value,
e^-t/RC.

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This is our standard equation
to which we plug in,

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and it's either a rising
exponential if VI is larger than

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VC or a decaying exponential if
VI is a smaller value than VC.

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This should all be familiar.
And, again, as pointed out in

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the notes, the reading for today
is 10.3 and for the new material

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you should look at Chapter 11
where we discuss memory.

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This is where we stood as of
last time.

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Now, I would like to discuss a
little bit more about the

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storage of charge in capacitors.
And how we can take advantage

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of that for storing logic state.
One of the things that I am

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sure you must be aware of is
that one of the perhaps most

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massively produced chips is
actually the so-called DRAM

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which you find in every PC and
every computer that exists

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anywhere.
This DRAM is dynamic random

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access memory in which we can
store a state and come back and

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look at it at any time later,
provided we don't power off our

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machine.
The logic state in the basic

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memory elements,
of which instead there are

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close to 1 giga elements per
chip, are stored on capacitors.

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And so we will play a little
bit with that concept today.

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And, although we're not going
to discuss the specific example

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of the DRAM, the basic elements
of the DRAM you will see

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00:04:56,000 --> 00:05:04,000
actually in a demo shortly.
So that's the general response

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of this network that I have here
to an input VI that happens at

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t=0.
Now, the one thing that you

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recognize immediately is that it
really doesn't matter what the

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value of VI was for t less than
zero.

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00:05:38,000 --> 00:05:43,000
What really counts is the value
of VI at t=0.

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00:05:43,000 --> 00:05:48,000
And that's the value that we're
interested in.

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Now, there is an implicit
statement in that.

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And that statement is that
somehow that network appears

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like this at t=0.
So, there has to be some switch

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there, and you will see that,
that basically starts my

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condition to that at t=0.
And so the history of VI really

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doesn't matter.
The response following that

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00:06:27,000 --> 00:06:35,000
equation that we have there will
depend on the initial value

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which is vc(0) here.
Now that is the voltage on the

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capacitor at that time.
And then assuming that VI is a

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value that is larger than vc(0)
will have a rising exponential

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that will come to this value.
And this is the time constant

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RC and this is time.
So, the capacitor starts with

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00:07:12,000 --> 00:07:23,000
some voltage here and goes to a
new voltage that is imposed by

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the input for time greater than
zero.

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We can define at any one time,
say this time,

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this time, this time,
this time the state of the

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capacitor.
The state.

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What is the state of the
capacitor?

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The state is the summary of all
inputs that are relevant to

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predicting the future.
If I know the state of the

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capacitor this time,
I can predict what it is going

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to go given a response VI here
in the future.

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So, predicts the future.
Now, what is the state variable

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on the capacitor?
What is actually stored on the

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capacitor?
You can say,

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well, what is stored is
voltage.

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00:08:30,000 --> 00:08:36,000
The real physical quantity that
is stored is the charge q which

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is for linear capacitors related
to the voltage,

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let me actually write it
correctly, vc like this.

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00:08:44,000 --> 00:08:48,000
So, the real state variable is
this.

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00:08:57,000 --> 00:09:05,000
But for a linear capacitor,
since there is one-to-one

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relationship between the two,
v is also a state variable.

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00:09:13,000 --> 00:09:21,000
OK, so let's then go back to
our original circuit.

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00:09:21,000 --> 00:09:25,000
What we have is --

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00:09:37,000 --> 00:09:45,000
-- vc(t), so that's the future
value of the voltage on the

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00:09:45,000 --> 00:09:53,000
capacitor, is a function of
vc(0), the initial value and the

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00:09:53,000 --> 00:10:00,000
variable input now in the future
time.

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00:10:00,000 --> 00:10:08,000
And for the case of vI(t) being
constant VI for t greater or

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equal than zero we have the
equation that we just described.

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Nothing new.

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00:10:30,000 --> 00:10:36,000
All the past inputs to the
capacitor for time t less or

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00:10:36,000 --> 00:10:41,000
equal to zero is summarized in
this value.

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00:10:41,000 --> 00:10:47,000
And vi being constant the
future is predicted from that.

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00:10:47,000 --> 00:10:51,000
So, that's the concept of the
state.

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00:10:51,000 --> 00:10:58,000
There is an initial state on
the capacitor.

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00:10:58,000 --> 00:11:04,000
And then there is a final state
that will be reached when

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equilibrium actually is
achieved.

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00:11:07,000 --> 00:11:13,000
There is a fair amount of
discussion in the text,

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and we don't go in great detail
here, but it is both convenient

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for analysis and also it's
interesting in many cases to

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look at the response of a linear
network for two different

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conditions.
So, we're interested in two

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cases.
One is the so-called zero state

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response.
Now, what is the zero state

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response?
It's the response to a

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condition in which we impose an
input and impose also the

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condition that the initial
value, initial state of the

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capacitor is zero.
So then we ask how does it

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respond to vi(t)?
So, starting with a capacitor

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00:12:36,000 --> 00:12:40,000
at zero state what is the
response?

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00:12:40,000 --> 00:12:46,000
It allows us to decouple the
initial conditions from the

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00:12:46,000 --> 00:12:51,000
response to the input.
Now, you will see that this is

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actually very useful.
The second condition to which

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we're also very interested is
the so-called zero input

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response.
What is that?

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That is vi(t)=0.
Now, it's the condition under

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00:13:18,000 --> 00:13:26,000
which there is no input.
vi(t)=0.

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00:13:26,000 --> 00:13:38,000
The question here is how does
it relax?

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We're starting with an initial
state.

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So, how this state relaxes out
in the circuit.

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Now, the zero state response,
this one here is Z so called SR

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for our case,
which I will write like this,

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00:14:02,000 --> 00:14:09,000
vC, ZSR is simply a rising
exponential.

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00:14:09,000 --> 00:14:16,000
We start from zero and we go to
VI.

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00:14:16,000 --> 00:14:24,000
So, it's VI-VI e^-t/RC.
So, that's the ZSR.

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00:14:24,000 --> 00:14:35,000
The ZIR, the zero input
response is like this.

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It's the decay of the initial
voltage on the capacitor to zero

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or to equilibrium.
Starting from vC(0) we're

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decaying like this.
Now, do you see something

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that's rather obvious from
what's on the board in terms of

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ZIR and ZSR and the final
complete answer which is there?

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00:15:18,000 --> 00:15:21,000
They are specific cases,
but how do they relate to the

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00:15:21,000 --> 00:15:23,000
full answer?
It's the sum.

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It's the superposition of the
two.

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What basically we see here --
And that's actually a general

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statement, is that vC = vC,ZSR +
vC,ZIR.

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00:15:39,000 --> 00:15:48,000
Now, you may say this is
trivial because we started from

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that, ended back in that from
some very simple observations.

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00:15:59,000 --> 00:16:04,000
However, we are not always
solving networks for responses

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00:16:04,000 --> 00:16:08,000
that are steps.
The input voltage may be a

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00:16:08,000 --> 00:16:11,000
ramp.
We did that in recitation.

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Or, it could be an impulse.
Or, it can be a more

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complicated function.
Having this observation in

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place actually allows us to
solve the problem rather neatly.

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If I have time at the end,
I might come back to this.

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So, this is the same equation
as I started with,

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arrived at from a principle of
superposition of two different

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00:16:43,000 --> 00:16:47,000
solutions.
One application of state which

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can be, since we have energy
storage element here,

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the capacitor,
which can be stored on the

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capacitor is in memory.
And you may ask,

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so why do we need a memory node
to perform logic?

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00:17:05,000 --> 00:17:11,000
Well, there are cases in which
a result depends on previous

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results.
So, a computation proceeds in

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time.
In order to do that,

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we need to store intermediate
results and proceed forward.

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One good example is if you're
doing a continuous summation,

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say, on your calculator,
you keep putting things in the

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memory.
The M+ button,

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right?
And you keep adding a series of

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numbers.
Every time we store the sum of

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the previous operation we add
another number and so on.

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Clearly we need some way of
storing state.

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For a complete computing
system, we need combinational

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logic and we need memory.
In fact, these are the two

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basic elements that are
essential for any kind of

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computing system.
We need to remember

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intermediate results.
We need to remember transient

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inputs.
And that's the role that all

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these enormous amount of memory
that comes to play in computers

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is doing.
The basic memory abstraction is

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as follows.

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Imagine a block which needs to
be populated by transistor,

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resistor, capacitor,
whatever elements.

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And it has a control input,
which we will call the store.

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It has a state input that we
will call dIN and has an output

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dOUT.
When we're telling this

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00:19:12,000 --> 00:19:20,000
element, OK, now it's time to
store, it looks at the input dIN

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and stores it for,
in principle,

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an infinite amount of time.
If we were to make a drawing of

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this, of what this looks like,
let's suppose,

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00:19:40,000 --> 00:19:47,000
let me do all this in one axis.
So, time moves this way.

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Let's suppose that we have an
input dIN that looks like this,

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00:19:56,000 --> 00:20:04,000
and the store command comes in
the form of a logic.

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00:20:04,000 --> 00:20:08,000
Let's actually suggest here
this is logic one,

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00:20:08,000 --> 00:20:13,000
this is logic zero.
And, although this is not

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00:20:13,000 --> 00:20:17,000
absolutely necessary,
let's also define that the

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00:20:17,000 --> 00:20:23,000
store command comes in the form
of a logic one at this store

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00:20:23,000 --> 00:20:26,000
input.
Store, let's say,

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00:20:26,000 --> 00:20:29,000
looks like this.

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00:20:34,000 --> 00:20:41,000
What does the output look like
then in this particular case?

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00:20:41,000 --> 00:20:49,000
Assuming that the output was
dOUT, the stored element was

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00:20:49,000 --> 00:20:56,000
zero prior to the store,
then the output would look like

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00:20:56,000 --> 00:21:00,000
this.
This is dOUT.

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00:21:00,000 --> 00:21:04,000
As you can see,
it would remember the one that

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00:21:04,000 --> 00:21:09,000
it saw at this point.
In fact, it would do that

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00:21:09,000 --> 00:21:15,000
irrespective of what was stored
in this memory cell.

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00:21:15,000 --> 00:21:19,000
For example,
suppose it was storing one and

202
00:21:19,000 --> 00:21:23,000
the output didn't change,
it's still one.

203
00:21:23,000 --> 00:21:30,000
If it was storing a zero,
it would flip to a one.

204
00:21:30,000 --> 00:21:34,000
If we had another store,
let's say here,

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00:21:34,000 --> 00:21:40,000
then what happens?
Then it would go back down to

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00:21:40,000 --> 00:21:47,000
zero because now we sampled an
input that is zero and we

207
00:21:47,000 --> 00:21:54,000
flipped the state.
That's what a memory --

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00:22:01,000 --> 00:22:04,000
-- element or cell would do for
us.

209
00:22:04,000 --> 00:22:08,000
It would remember the output
state.

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00:22:08,000 --> 00:22:13,000
And, not only that,
but in principle it should be

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00:22:13,000 --> 00:22:17,000
undisturbable.
In other words,

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00:22:17,000 --> 00:22:23,000
I may do something to this dOUT
but it should not flip the

213
00:22:23,000 --> 00:22:27,000
state.
And that comes about quite a

214
00:22:27,000 --> 00:22:31,000
bit.
Because in actual integrated

215
00:22:31,000 --> 00:22:35,000
circuit memory there is lots and
lots and lots of nearest

216
00:22:35,000 --> 00:22:39,000
neighbors to this cell which,
when they're flipped,

217
00:22:39,000 --> 00:22:42,000
have a cross-coupling to the
cell.

218
00:22:42,000 --> 00:22:46,000
The cell must be designed
robust enough that it doesn't

219
00:22:46,000 --> 00:22:49,000
flip, that no coupling actually
occurs.

220
00:22:49,000 --> 00:22:53,000
All right.
Now we're going to try to apply

221
00:22:53,000 --> 00:22:59,000
what we've learned so far to
invent a basic memory element.

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00:22:59,000 --> 00:23:07,000
And, believe it or not,
this is the key to the DRAM.

223
00:23:14,000 --> 00:23:18,000
Let's implement this in a
circuit.

224
00:23:24,000 --> 00:23:29,000
Suppose I have a switch here
like this.

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00:23:34,000 --> 00:23:42,000
And I will put a capacitor.
I take my dOUT here.

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00:23:42,000 --> 00:23:50,000
This is dIN.
And the switch is operated by a

227
00:23:50,000 --> 00:23:56,000
command here that we will call
store.

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00:23:56,000 --> 00:24:06,000
When store is one it goes up.
When store is zero it is down

229
00:24:06,000 --> 00:24:10,000
here.
That's capacitor C.

230
00:24:10,000 --> 00:24:14,000
This is the storage node.

231
00:24:24,000 --> 00:24:27,000
What are we actually storing in
this case?

232
00:24:27,000 --> 00:24:31,000
Let's suppose that this voltage
here is 5 volts.

233
00:24:31,000 --> 00:24:37,000
I flip the switch up to one and
I flip it back down to zero.

234
00:24:37,000 --> 00:24:41,000
What's the voltage in this
capacitor here?

235
00:24:41,000 --> 00:24:44,000
5 volts.
Now the capacitor is at 5

236
00:24:44,000 --> 00:24:50,000
volts, I put dIN to ground,
flip the switch back up and

237
00:24:50,000 --> 00:24:55,000
then back down to its known
storing condition.

238
00:24:55,000 --> 00:25:00,000
What's the voltage in the
capacitor?

239
00:25:00,000 --> 00:25:04,000
It's zero, exactly.
So, it does store the value of

240
00:25:04,000 --> 00:25:08,000
the voltage that it saw,
five or zero,

241
00:25:08,000 --> 00:25:12,000
high and low.
It stores it because it stores

242
00:25:12,000 --> 00:25:15,000
charge.
That's actually the physical

243
00:25:15,000 --> 00:25:20,000
quantity that's stored.
It's manifested as a voltage,

244
00:25:20,000 --> 00:25:22,000
which we see.
All right.

245
00:25:22,000 --> 00:25:28,000
Now, is this,
oh, before I move from here.

246
00:25:28,000 --> 00:25:33,000
What is the basic cell in a
DRAM, one that you go out and

247
00:25:33,000 --> 00:25:37,000
buy by the billions of cells?
It's actually this.

248
00:25:37,000 --> 00:25:43,000
The only difference is that
this switch here is replaced

249
00:25:43,000 --> 00:25:45,000
with a MOSFET.

250
00:25:50,000 --> 00:25:54,000
And that's all it is.
So, a MOSFET plays the role of

251
00:25:54,000 --> 00:25:57,000
the switch.
When the gate is high this is a

252
00:25:57,000 --> 00:26:02,000
resistor and connects the input
to the capacitor.

253
00:26:02,000 --> 00:26:07,000
And when the gate voltage is
below the threshold voltage this

254
00:26:07,000 --> 00:26:12,000
is an open, as we've seen,
and it isolates the transistor

255
00:26:12,000 --> 00:26:16,000
from the output.
So, that's the basic memory

256
00:26:16,000 --> 00:26:18,000
element.

257
00:26:28,000 --> 00:26:33,000
And, as I said,
it's the key to a DRAM.

258
00:26:33,000 --> 00:26:37,000
OK.
Now let's consider a little bit

259
00:26:37,000 --> 00:26:42,000
the conditions of operation of
this thing.

260
00:26:42,000 --> 00:26:47,000
Let me draw the circuit in two
conditions.

261
00:26:47,000 --> 00:26:55,000
One in which it is storing,
one in which it is sampling and

262
00:26:55,000 --> 00:27:04,000
one in which it is storing.
Not to redraw this thing.

263
00:27:04,000 --> 00:27:14,000
Assuming that I have a MOSFET
there, I would have the on

264
00:27:14,000 --> 00:27:20,000
resistance in place here when
store=1.

265
00:27:20,000 --> 00:27:30,000
Now, in principle,
the output is connected to --

266
00:27:36,000 --> 00:27:40,000
-- some load resistance.
We'll talk a little bit more

267
00:27:40,000 --> 00:27:44,000
about this load resistance in a
minute.

268
00:27:44,000 --> 00:27:49,000
This is the situation when we
are at store=1 situation.

269
00:27:49,000 --> 00:27:53,000
For example,
let's suppose that dIN is 5

270
00:27:53,000 --> 00:27:56,000
volts.
Now, what is the situation for

271
00:27:56,000 --> 00:28:00,000
store=0?
It's very simple.

272
00:28:00,000 --> 00:28:12,000
We have the capacitor C and
dOUT and here we have a

273
00:28:12,000 --> 00:28:20,000
resistance.
The switch is open.

274
00:28:20,000 --> 00:28:31,000
This is store=0 condition.
What we have in this case is we

275
00:28:31,000 --> 00:28:37,000
have a problem similar to what I
was discussing earlier.

276
00:28:37,000 --> 00:28:39,000
It is a ZIR,
if you like,

277
00:28:39,000 --> 00:28:44,000
situation.
And this you can think of as a

278
00:28:44,000 --> 00:28:50,000
ZSR if we're starting with zero
charge on the capacitor,

279
00:28:50,000 --> 00:28:53,000
but I'm interested in this
part.

280
00:28:53,000 --> 00:28:57,000
In this case,
I am starting with a vC(0)=5

281
00:28:57,000 --> 00:29:02,000
volts.
And I'm asking myself how long

282
00:29:02,000 --> 00:29:06,000
will this cell hold the value?
And, in fact,

283
00:29:06,000 --> 00:29:10,000
that is actually what happens
in a dynamic RAM.

284
00:29:10,000 --> 00:29:15,000
The value on the capacitor is
not stored forever.

285
00:29:15,000 --> 00:29:20,000
In fact, that's why we call it
dynamic because we have to come

286
00:29:20,000 --> 00:29:24,000
back and restore it every once
in a while.

287
00:29:24,000 --> 00:29:30,000
For how long are we going to
store the charge?

288
00:29:30,000 --> 00:29:37,000
What's the response of vc for t
greater than zero after the

289
00:29:37,000 --> 00:29:41,000
switch flicked?
It's very simple.

290
00:29:41,000 --> 00:29:48,000
It's vc is equal to 5 volts e
to the minus t over RC,

291
00:29:48,000 --> 00:29:52,000
right?
That's the response.

292
00:29:52,000 --> 00:29:58,000
We have a decay.
And applying to the things we

293
00:29:58,000 --> 00:30:02,000
know.
We start from 5 volts,

294
00:30:02,000 --> 00:30:07,000
let's say here,
I have a decay going down

295
00:30:07,000 --> 00:30:12,000
towards zero,
at some point we are going to

296
00:30:12,000 --> 00:30:19,000
cross the threshold for high.
The only period in which I have

297
00:30:19,000 --> 00:30:24,000
a valid output,
if the capacitor was storing a

298
00:30:24,000 --> 00:30:32,000
one, is this period here.
This is the only period in

299
00:30:32,000 --> 00:30:39,000
which I have valid stored one
because, once I go beyond

300
00:30:39,000 --> 00:30:46,000
capital T here,
I have crossed the legal limit,

301
00:30:46,000 --> 00:30:51,000
threshold for discriminating a
high output.

302
00:30:51,000 --> 00:30:59,000
And from then on the output is
no longer valid.

303
00:30:59,000 --> 00:31:05,000
So, this memory is good
provided time is less than

304
00:31:05,000 --> 00:31:10,000
capital T.
It's not a case in which the

305
00:31:10,000 --> 00:31:14,000
capacitor can hold charge
forever.

306
00:31:14,000 --> 00:31:21,000
In fact, we can calculate,
that is we can solve for T in

307
00:31:21,000 --> 00:31:28,000
this particular case.
It's in your notes.

308
00:31:28,000 --> 00:31:37,000
Nothing really profound.
T is equal to minus RC log VOH

309
00:31:37,000 --> 00:31:45,000
over 5 volts.
So, this is basically what the

310
00:31:45,000 --> 00:31:53,000
response is going to be.
Now, there is an implicit

311
00:31:53,000 --> 00:32:01,000
assumption here,
which is that the store pulse

312
00:32:01,000 --> 00:32:10,000
width is much,
much larger than RON C.

313
00:32:10,000 --> 00:32:13,000
In other words,
when we want to store a one

314
00:32:13,000 --> 00:32:16,000
here starting from zero,
we better charge it all the way

315
00:32:16,000 --> 00:32:21,000
up to 5 volts in the time that
our switch is connected here.

316
00:32:21,000 --> 00:32:23,000
And what is the relevant time
constant?

317
00:32:23,000 --> 00:32:27,000
It's going to be the RON C.
In fact, it's actually the RON

318
00:32:27,000 --> 00:32:33,000
parallel RL with C.
But typically RON is much,

319
00:32:33,000 --> 00:32:39,000
much less than RL so we don't
have to worry about that.

320
00:32:39,000 --> 00:32:42,000
Dominant time constant is RON
C.

321
00:32:42,000 --> 00:32:49,000
So, provided these things are
happening, we have a memory.

322
00:32:49,000 --> 00:32:55,000
Now, we can try to improve
things a little bit.

323
00:32:55,000 --> 00:33:01,000
We see here that we will have a
decay to an invalid state in

324
00:33:01,000 --> 00:33:07,000
time T.
How can we improve things?

325
00:33:07,000 --> 00:33:12,000
One way to improve things are
the buffer.

326
00:33:12,000 --> 00:33:16,000
Here is our memory element
again.

327
00:33:16,000 --> 00:33:22,000
Here is the capacitor.
This is the storing node.

328
00:33:22,000 --> 00:33:29,000
Now I am going to put the
buffering effect.

329
00:33:29,000 --> 00:33:33,000
I am going to put two buffers
here.

330
00:33:33,000 --> 00:33:36,000
Two invertors,
I should say,

331
00:33:36,000 --> 00:33:43,000
because if I am storing a one
here I want to be able to see a

332
00:33:43,000 --> 00:33:48,000
one here as well.
And, in this case,

333
00:33:48,000 --> 00:33:53,000
what I am looking at is the RIN
of the buffer.

334
00:33:53,000 --> 00:34:00,000
And, in principle,
I have out here the RL.

335
00:34:00,000 --> 00:34:15,000
Now, this is better because if
RIN is much larger than RL then

336
00:34:15,000 --> 00:34:28,000
the time T, in this case,
is much larger than the case

337
00:34:28,000 --> 00:34:36,000
without buffer.
So, we buffer the effect of VL.

338
00:34:36,000 --> 00:34:42,000
This could be one of these neat
circuits we saw in recitation

339
00:34:42,000 --> 00:34:45,000
like a source faller,
for example,

340
00:34:45,000 --> 00:34:51,000
or it can be just an inverter
in which case you just see the

341
00:34:51,000 --> 00:34:57,000
input of a transistor.
So, now this condition can be

342
00:34:57,000 --> 00:35:03,000
satisfied.
Let me give you some cases

343
00:35:03,000 --> 00:35:11,000
which are some numbers that are
typical for a dynamic RAM.

344
00:35:11,000 --> 00:35:20,000
Typical times we're talking
about is RIN on order of 1

345
00:35:20,000 --> 00:35:27,000
gigaohm and storage node
capacitor on order of 1

346
00:35:27,000 --> 00:35:36,000
femtofarad to one picofarad.
Now, if you can do the math in

347
00:35:36,000 --> 00:35:41,000
your head, which is just
multiplication,

348
00:35:41,000 --> 00:35:47,000
you will see that the time
constant, the RC is between 1

349
00:35:47,000 --> 00:35:52,000
millisecond to 1 microsecond.
And for DRAMs,

350
00:35:52,000 --> 00:36:00,000
actually, we try to be in the
order of milliseconds.

351
00:36:00,000 --> 00:36:03,000
These are the times we're
talking about.

352
00:36:03,000 --> 00:36:07,000
If I have this kind of circuit,
somehow there has got to be

353
00:36:07,000 --> 00:36:12,000
additional circuitry that comes
back, samples the voltage here

354
00:36:12,000 --> 00:36:16,000
and restores it.
And that is actually what is

355
00:36:16,000 --> 00:36:20,000
happening in a DRAM.
And my laptop is working there

356
00:36:20,000 --> 00:36:23,000
and its DRAM keeps getting
refreshed every,

357
00:36:23,000 --> 00:36:28,000
say, millisecond or whatever
the condition is.

358
00:36:28,000 --> 00:36:32,000
But, in our case,
we are going to do a slightly

359
00:36:32,000 --> 00:36:38,000
different case in which we will
create a static memory.

360
00:36:38,000 --> 00:36:42,000
Let's actually look at,
first of all,

361
00:36:42,000 --> 00:36:47,000
the case of the discharge.
Pay attention to,

362
00:36:47,000 --> 00:36:50,000
let me actually break the loop
here.

363
00:36:50,000 --> 00:36:56,000
This is my capacitor.
This is a resistor that is in

364
00:36:56,000 --> 00:37:02,000
series with a capacitor like you
see here.

365
00:37:02,000 --> 00:37:07,000
Actually, I am going to keep
that resistor in series with the

366
00:37:07,000 --> 00:37:13,000
capacitor, even in this case,
because I have it for my second

367
00:37:13,000 --> 00:37:18,000
part of my example.
I charge the capacitor to 5

368
00:37:18,000 --> 00:37:21,000
volts.
And you can see here this

369
00:37:21,000 --> 00:37:26,000
lights up, I hope everybody can
see it, proportional to the

370
00:37:26,000 --> 00:37:32,000
voltage that I have here.
From here on it's all logic

371
00:37:32,000 --> 00:37:35,000
levels.
So, the intensity of light here

372
00:37:35,000 --> 00:37:39,000
will always be the same.
It's either lit or it's not

373
00:37:39,000 --> 00:37:42,000
lit.
Right now I am charging the

374
00:37:42,000 --> 00:37:44,000
capacitor.
In fact, let's see.

375
00:37:44,000 --> 00:37:49,000
Maybe I can discharge the
capacitor first.

376
00:37:58,000 --> 00:38:00,000
Here the capacitor is
discharged.

377
00:38:00,000 --> 00:38:03,000
As you can see,
the input is zero,

378
00:38:03,000 --> 00:38:08,000
the output is a one,
and then the output of this

379
00:38:08,000 --> 00:38:13,000
inverter here is a one.
I have two inverters in series.

380
00:38:13,000 --> 00:38:16,000
And I am going to charge the
capacitor.

381
00:38:16,000 --> 00:38:21,000
I charged it to 5 volts and
this lit up, this is off of

382
00:38:21,000 --> 00:38:26,000
course, that's an inverter,
this is a valid zero,

383
00:38:26,000 --> 00:38:30,000
produce a valid one.
And now I am going to take the

384
00:38:30,000 --> 00:38:35,000
input out.
As you can see it's stored.

385
00:38:35,000 --> 00:38:38,000
In fact, we have to wait for a
very long time.

386
00:38:38,000 --> 00:38:42,000
We don't have enough time to
wait for this to discharge,

387
00:38:42,000 --> 00:38:47,000
so instead what I am going to
do now is I am going to add also

388
00:38:47,000 --> 00:38:50,000
the resistor.
Now I am going to flip the

389
00:38:50,000 --> 00:38:54,000
resistor in parallel with the
capacitor to imitate what

390
00:38:54,000 --> 00:38:59,000
happens when we have an input
resistance.

391
00:38:59,000 --> 00:39:04,000
You saw that there was a
discharge of the capacitor.

392
00:39:04,000 --> 00:39:10,000
This input level went down.
Voltage here flipped over to a

393
00:39:10,000 --> 00:39:14,000
one.
Let me do it again now with a

394
00:39:14,000 --> 00:39:18,000
resistor in place.
Storing charge on the

395
00:39:18,000 --> 00:39:22,000
capacitor.
That's the store command.

396
00:39:22,000 --> 00:39:25,000
Now, don't store.
I have less,

397
00:39:25,000 --> 00:39:30,000
about a second.
The element here is 20,000

398
00:39:30,000 --> 00:39:36,000
microfarads and 100 ohms which
gives me a time constant of two

399
00:39:36,000 --> 00:39:40,000
seconds.
Assuming a VOC of the order of,

400
00:39:40,000 --> 00:39:45,000
let's say, I don't know what it
is for this case,

401
00:39:45,000 --> 00:39:51,000
2.5, the log would be about
0.5, so it cuts basically the

402
00:39:51,000 --> 00:39:56,000
time to about one.
So, it lasts about one second,

403
00:39:56,000 --> 00:40:03,000
if my math is all correct.
It's actually a little longer

404
00:40:03,000 --> 00:40:08,000
than a second,
excuse me, but the point is

405
00:40:08,000 --> 00:40:13,000
that the charge is gone.
Now, notice,

406
00:40:13,000 --> 00:40:19,000
however, that there is
something I can do here,

407
00:40:19,000 --> 00:40:27,000
which is that suppose I take
the switch or a switch and bring

408
00:40:27,000 --> 00:40:36,000
it back and provide a path from
the output to the input here.

409
00:40:36,000 --> 00:40:41,000
And this switch is open when
this is closed and closed when

410
00:40:41,000 --> 00:40:45,000
this is open.
So, this basically is the

411
00:40:45,000 --> 00:40:50,000
compliment of store.
What I am doing now is I put a

412
00:40:50,000 --> 00:40:55,000
charge here, it produces a valid
one at this point,

413
00:40:55,000 --> 00:41:02,000
and then I am feeding this
valid one back to the input.

414
00:41:02,000 --> 00:41:06,000
As you can see,
this will now allow me,

415
00:41:06,000 --> 00:41:12,000
even though I have a high
resistance, to store the value

416
00:41:12,000 --> 00:41:15,000
for a long time.
In this case,

417
00:41:15,000 --> 00:41:21,000
what I am going to do is I am
going to connect the output,

418
00:41:21,000 --> 00:41:26,000
as you can see here.
And I have my resistor in.

419
00:41:26,000 --> 00:41:32,000
And I am storing zero here,
storing 5 volts.

420
00:41:32,000 --> 00:41:36,000
Now I am going to flip the
switch.

421
00:41:36,000 --> 00:41:43,000
Basically, I mean the don't
store, don't look case.

422
00:41:43,000 --> 00:41:48,000
You notice this dims a little
bit.

423
00:41:48,000 --> 00:41:54,000
Sorry.
No, I want the resistor in.

424
00:42:11,000 --> 00:42:12,000
There.
Yes.

425
00:42:12,000 --> 00:42:18,000
OK, so the output remain value.
This dimmed a little bit but

426
00:42:18,000 --> 00:42:22,000
the output has remained OK.
All right.

427
00:42:22,000 --> 00:42:29,000
So, we've provided a feedback.
Now we've created a static

428
00:42:29,000 --> 00:42:33,000
memory.
This will hold charge for as

429
00:42:33,000 --> 00:42:37,000
long as the circuit is powered
up.

430
00:42:37,000 --> 00:42:43,000
Now, there is still one little
problem that I have with this

431
00:42:43,000 --> 00:42:49,000
kind of configuration.
And that is if I disturb this

432
00:42:49,000 --> 00:42:53,000
output the charge may,
the state may change.

433
00:42:53,000 --> 00:42:59,000
So, for example,
let's say that I have --

434
00:42:59,000 --> 00:43:07,000
I disturbed it by coming close
to it, so let's charge it again.

435
00:43:14,000 --> 00:43:15,000
OK.
I flipped the switch.

436
00:43:15,000 --> 00:43:18,000
I flipped the state from the
output.

437
00:43:18,000 --> 00:43:23,000
That is an invalid condition.
I shouldn't be able to do that.

438
00:43:23,000 --> 00:43:26,000
How do I avoid that?
How can I avoid this problem

439
00:43:26,000 --> 00:43:29,000
that you just saw?

440
00:43:34,000 --> 00:43:36,000
Well, I need yet another
buffer.

441
00:43:36,000 --> 00:43:42,000
The answer is in your notes.
If I don't take the output here

442
00:43:42,000 --> 00:43:48,000
but rather take the output here,
or if I don't want an inverted

443
00:43:48,000 --> 00:43:52,000
output, if I don't want an
inverted output,

444
00:43:52,000 --> 00:43:55,000
I could put yet another element
there.

445
00:43:55,000 --> 00:44:00,000
Then the situation would be
fine.

446
00:44:00,000 --> 00:44:03,000
In this case,
let me do it again.

447
00:44:03,000 --> 00:44:05,000
Charge.

448
00:44:17,000 --> 00:44:18,000
Why isn't this lit?

449
00:44:24,000 --> 00:44:25,000
A bad one?

450
00:44:35,000 --> 00:44:38,000
Now, of course we disturbed the
input.

451
00:44:38,000 --> 00:44:42,000
Now, of course I can do
anything I want here.

452
00:44:42,000 --> 00:44:46,000
Nothing happens,
but you may say this is a

453
00:44:46,000 --> 00:44:50,000
trivial case because this is
already zero.

454
00:44:50,000 --> 00:44:53,000
So, I am going to change the
state.

455
00:44:53,000 --> 00:44:56,000
Here's is the changed state.
See.

456
00:44:56,000 --> 00:45:01,000
I can show this.
Nothing happens up there.

457
00:45:01,000 --> 00:45:05,000
So, this is an interesting
situation in which I am

458
00:45:05,000 --> 00:45:10,000
buffering the output so that the
output does not feed back to the

459
00:45:10,000 --> 00:45:12,000
input.
And, by and large,

460
00:45:12,000 --> 00:45:17,000
in designing circuits this is
something that we do.

461
00:45:17,000 --> 00:45:22,000
Now, in the remaining three
minutes there is an example that

462
00:45:22,000 --> 00:45:26,000
we have.
Can we put the laptop here?

463
00:45:38,000 --> 00:45:43,000
OK, so here is an example of
how memory can be put together

464
00:45:43,000 --> 00:45:48,000
now to create something a little
bit more complicated.

465
00:45:48,000 --> 00:45:53,000
And you can see the memory
cells that we were discussing

466
00:45:53,000 --> 00:45:56,000
here.
There's four of them,

467
00:45:56,000 --> 00:46:02,000
so this is a four bit memory.
There is a decoder at the

468
00:46:02,000 --> 00:46:08,000
beginning here which decodes the
address of each cell,

469
00:46:08,000 --> 00:46:14,000
so the input here will tell me
which cell I need to address.

470
00:46:14,000 --> 00:46:20,000
Let's look at the truth table.
This is the truth table for the

471
00:46:20,000 --> 00:46:22,000
decoder.
As you can see,

472
00:46:22,000 --> 00:46:28,000
depending on the address that I
have here, this is zero,

473
00:46:28,000 --> 00:46:33,000
one, two and three in a binary
system, only A,

474
00:46:33,000 --> 00:46:37,000
B, C or D is up,
is high.

475
00:46:37,000 --> 00:46:42,000
Which means that this end
operation here only allows the

476
00:46:42,000 --> 00:46:46,000
input that is presented to all
of the cells,

477
00:46:46,000 --> 00:46:51,000
what is going through the AND
gate here to appear at the

478
00:46:51,000 --> 00:46:53,000
output.
If, for example,

479
00:46:53,000 --> 00:46:57,000
we have a one,
zero, the only end input that

480
00:46:57,000 --> 00:47:03,000
is going to be high is going to
be this one.

481
00:47:03,000 --> 00:47:08,000
And that means the only cell
that will look at the input when

482
00:47:08,000 --> 00:47:12,000
the store comes up is going to
be this one here.

483
00:47:12,000 --> 00:47:18,000
At that point it will store
whatever is on the input cell

484
00:47:18,000 --> 00:47:23,000
because that's an AND operation.
That is a simple example of a

485
00:47:23,000 --> 00:47:46,000
memory.
And following that simple

486
00:47:46,000 --> 00:48:36,000
arrangement you can build
incredibly large memory systems.

487
00:48:36,000 --> 00:48:39,000
So, that's all I had for today.
And I will see you on Tuesday.