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All right, let's get moving.
Good morning.

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Let me take a quick poll.
So, how many of you have

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completed Lab 4.
Completed Lab 4?

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Wow, that's great.
So, how many people have begun

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Lab 4?
OK, well that's good.

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I won't ask the last question.
OK so, well I hope you're

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having fun with this lab.
Lab 4 was designed to be almost

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like a mini-project.
And, it sort of ties together a

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lot of the content of the entire
course.

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And, it's not unlike the kind
of systems that people design in

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industry, in systems that go
into a variety of devices like,

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say, for example,
digital CD players and stuff

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like that.
A lot of mixed signal stuff

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goes in.
OK, so today,

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I'm going to continue with our
discussion of energy and CMOS.

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CMOS will be a new topic that I
will introduce.

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So, the last lecture,
we spent a fair bit of time

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talking about energy,
and how to compute the energy

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of our inverter.
So, let me start from where I

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left off, and I've given you a
couple of extra pages of notes

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today just to sort of tie it to
the previous lecture.

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Right now, I'm going to start
off on page three.

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So, what we saw last time was
an inverter of this sort,

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Vs, VIN, and we said,
let's study the situation where

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this inverter was driving a load
capacitor, C.

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Where did this load capacitor
come from?

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Well, this inverter could be
driving one, or two,

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or three, or four other larger
gates, OK?

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So, this C is lumped value of
the gate capacitances of all of

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those inverters.
This may also include some

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component due to wiring
capacitance and stuff like that.

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So, for an inverter like this,
we showed in the last lecture

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that the formula for the average
power was,

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so this was a static power
independent of frequency,

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and this was called dynamic
power, and it had some bearing,

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it's related to the frequency
at which you clocked your

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circuit.
So, this was related to standby

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power, and this to dynamic.
So, what I also said is that I

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gave you a bunch of numbers so
you could compute the power

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consumption of a chip that
included 10^8 gates,

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100 million gates,
and at a frequency of 1 GHz,

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and a bunch of other numbers.
C was given to be 0.1

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femtofarads.
Femto is 10^-15.

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So, F was 10^9.
VS was 5V, and for these

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numbers, if you plonk them down
in something like this,

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for 10^8 gates on a chip,
the average power would be 10^8

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times these two.
So, this would be five squared,

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which is 25,
divided by twice.

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RL was given to be 10
kilo-ohms, so,

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twice, 10^4.
And here we had CVS^2.

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So, C was 10^-16,
0.1 femtofarads.

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Vs^2 was 25,
and F was 10^9.

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So, if you commence through the
numbers here,

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what you end up getting is
something that looks like this,

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10^8 times this guy here.
This is 1.25mW plus this guy

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ends up being 2.5 microwatts.
So, this should come as a bit

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of a shocker.
If I take 1.25mW,

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and multiply that out by 10^8,
this says that each gate

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suffers a standby power loss of
1.25mW.

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So times 10^8,
I get 125kW,

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and this guy yields 250W.
OK, the 250W is manageable.

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It's still high,
and just so you don't think

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that this is unreasonable,
when the Pentium 4 first came

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out, it was consuming 170W of
power.

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OK, you should see the heat
sinks on there.

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There's actually a huge heat
sink with a fan built into the

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top of the heat sink.
OK, today it's down to more

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reasonable numbers like 100W and
so on, but when it came out it

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was in this range.
So it's high but not

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unreasonable.
But this, of course,

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is totally wacko.
OK, imagine carrying a laptop

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around, and the sucker is
blowing 125kW.

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That'll be fun.
So, clearly there's something

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wrong here.
What this is saying is that

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this gate here consumes 125kW,
there are 10^8 of these on a

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single chip.
OK, so we clearly have to do

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something about this,
otherwise the semiconductor

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industry would fail.
So, anybody have any ideas?

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What do you think you might do
here?

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What do you think you might do
to this inverter to make this

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look better, to bring it down?
What can I do?

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Anybody?
Any ideas?

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What do you think?
Well, the problem is that if I

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look at this 125kW,
well, there's a VS term here

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and an RL term here.
So, I can increase RL.

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OK, I can make RL four times or
eight times as large.

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That'll bring the power down
somewhat.

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Can anybody think of any
problem with increasing RL?

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If I make RL really,
really large,

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will I run into other problems?
Yes?

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Exactly, the slowdown of the
inverter.

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Remember, the rise time of the
inverter depends on how quickly

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I can charge this capacitor
through RL.

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So, if I make my RL really
large, I will consume less

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standby power from hundreds of
kilowatts to merely tens of

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kilowatts.
But my gates will run as slow

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as molasses.
So, clearly that's not a

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tradeoff I would like to make.
So, I can reduce my voltage to

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maybe a volt.
But that just reduces it by a

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factor of 25,
VS squared.

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So clearly, this is not going
to work.

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I have to somehow do something
else, and that will be the topic

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of today's lecture.
Also, I will dwell for a moment

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on this term.
So, if you look at the spec

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sheet for the IBM's ASIC
processor that we handed out,

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if you recall,
we talked about power

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dissipation of 0.006 microwatts
per MHz per gate.

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OK, now you see where this is
coming from.

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Per MHz, that's because it's a
multiple of f,

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the power.
Second is that it's per gate,

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so this is the power per gate.
So, as I have more gates,

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I just have that much more
power dissipation.

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It also says power supply
voltage in the range of 0.7 to

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1.3 right next to the power
expression.

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So, you can see why they tell
you all of that,

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because both voltage,
and the frequency,

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and the number of gates come
into the power of equation.

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OK, this really simple
expression here,

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it's amazing how close this is
to what people use for the

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dynamic power in chips.
OK, so as the next step,

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what I'd like to do is,
this guy, what do we do about

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that?
OK, so we've taught you to

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build gates in a particular
matter, but it's a non-starter.

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So, how do we get rid of static
power?

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How do we get rid of static
power?

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OK, to do so,
let's build up a little bit of

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intuition.
OK, so the intuition goes as

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follows.
So let's say I take my

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inverter.
Let me draw the circuit both on

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the on state and in the off
state.

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So, when VIN is high,
when VIN is high,

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I get the MOSFET turning on and
has a resistance,

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RON, and Vo is the output
voltage.

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Similarly, when VIN is low,
so when VIN was high,

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Vo was low because RON is much
less than RL.

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So, this voltage was low,
while here, when VIN is low,

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the MOSFET is off,
and so I have an open circuit

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out here.
And because of that open

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circuit, the voltage here was
going to be high because VS

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would simply appear there.
So let's tailor this and see if

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we can build up some intuition
as to what to do.

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So, when VIN is low,
I don't have any static power

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being dissipated because I don't
have a connection from VS to

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ground.
OK, the current,

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i, is zero.
And, VS simply appears at the

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output.
The reason this is so is have a

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switch here.
So when this is low,

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the switch opens up and cuts
the path from power to ground.

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This is a nice situation.
Here, when VIN was high,

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there was no switch that turns
off.

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Rather, I get a connection from
VS to ground.

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OK, so think about this
situation here.

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The insight here is,
just imagine if I could do the

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following.
Imagine if I could somehow

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magically elevate RL to be a
very, very, very large number,

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if I could make this so high as
to make the power really low

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only in the situation when the
input was high,

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OK?
So, imagine if I could do

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something like this.
Imagine I could open circuit

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this guy, RON,
so when VIN was high,

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if I could, instead of having
an RL here, what if somehow I

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could make this RL become
infinity?

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OK, so in this case,
output VO would be low.

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OK, I get many benefits by
doing this.

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One benefit is that,
look, I have opened this switch

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here so I don't have any standby
current.

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OK, the standby current is
zero.

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The second benefit is that my
output gets dragged down to

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ground, OK?
Out here, my output was VS

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multiplied by RON divided by the
sum of these two.

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Out here, I have a direct
connection to ground,

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and nothing to the power
supply, VS, and so therefore I

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have a nice, solid low.
So the question is that,

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can I get this situation?
OK, that is a key insight.

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So, imagine that somehow,
when this was high,

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I could get this to open up,
much like when this was low,

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I got this to open up.
OK, so think about it.

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So, the intuition is that what
I need instead of a resistor

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here, what if I have something
like the MOSFET that I have

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here?
So, I have a MOSFET here that

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turned off when VIN was low.
OK, what if I did the

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complementary thing?
What if I put in some kind of

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MOSFET here that would turn off
when VIN was high?

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OK, so, much like the MOSFET
turned off when VIN was low down

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here, imagine if I could find a
device that could turn off when

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VIN was high?
OK, this would be on,

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but this would be off.
So the behavior of this device

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would have to be complementary
to this device.

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So, we need some sort of a
switch to introduce this new,

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little MOSFET device with
slightly different properties,

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let me quickly review for you
the properties of the MOSFET

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that we know about,
so our N channel MOSFET,

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also called the NFET,
this is what we've been seeing

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all this while,
is drawn like this.

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I have a gate;
I have a drain;

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I have a source.
And this guy is on when VGS is

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greater than or equal to VT,
OK, and off when VGS is less

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than VT.
You saw this before,

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OK, nothing new here.
So, what I need is a device

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that behaves in a complementary
manner.

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OK, so the device is a P
channel MOSFET.

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00:16:13,000 --> 00:16:19,000
By the way, I must point out,
till about 1983-84 until the

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early '80s, that's exactly
pretty much how chips were

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designed, OK,
using an NFET for the switch

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00:16:29,000 --> 00:16:34,000
looking down here,
and a variety of different

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kinds of devices to be used as
resistors.

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00:16:40,000 --> 00:16:44,000
OK, that's when technology
began moving towards this new

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kind of technology I'm going to
talk about, and that

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dramatically reducing the power
consumed.

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And, the P channel MOSFET was
created, and this guy's called

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the PFET.
It's a complementary device

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that looks as follows.
OK, the difference here is

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that, to show this is
complementary,

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I'll put a little circle here.
It has a gate.

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Just to make things a little
clearer, flip the drain and

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source terminals,
and this guy is on at a

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distinguished threshold voltage
of this with the NFET device,

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let me put an N here to say
that this is the VT for the N

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channel device.
And for this guy,

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this guy came on when VGS was
greater than some voltage.

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So, VTN could be,
for example,

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one volt.
So, VGS was more than one.

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This turned on.
In this case,

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I wanted this to turn on when
VGS is some value which is lower

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than, or much lower than,
the source voltage.

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OK, so this guy turns on when
the gate voltage is higher.

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00:18:00,000 --> 00:18:03,000
This guy should turn on when
the gate voltage is

228
00:18:03,000 --> 00:18:07,000
significantly lower than the
source voltage,

229
00:18:07,000 --> 00:18:10,000
just the complementary
behavior.

230
00:18:10,000 --> 00:18:13,000
OK, so when VGS is less than or
equal to VTP.

231
00:18:13,000 --> 00:18:17,000
And in this case,
the threshold voltage for the

232
00:18:17,000 --> 00:18:20,000
PMOS device, say,
just as an example,

233
00:18:20,000 --> 00:18:23,000
maybe -1V.
So this means that if the

234
00:18:23,000 --> 00:18:25,000
source is at,
say, 5V, OK,

235
00:18:25,000 --> 00:18:30,000
then this device would turn on
if the gate, for example,

236
00:18:30,000 --> 00:18:35,000
using that example was less
than 4V.

237
00:18:35,000 --> 00:18:39,000
So, this is five.
If the gate fell below 4V,

238
00:18:39,000 --> 00:18:43,000
this guy would turn on.
In this situation,

239
00:18:43,000 --> 00:18:49,000
remember, if this was at zero,
the gate would have to be

240
00:18:49,000 --> 00:18:53,000
greater than 1V to turn on.
In this situation,

241
00:18:53,000 --> 00:18:59,000
the gate has to be less than 4V
if the source was at five to

242
00:18:59,000 --> 00:19:03,000
turn on.
And, it's off.

243
00:19:03,000 --> 00:19:06,000
OK, so this is a complementary
device that I postulate that

244
00:19:06,000 --> 00:19:08,000
behaves in a complementary
manner.

245
00:19:08,000 --> 00:19:11,000
So, the gate voltage rises,
this guy turns on,

246
00:19:11,000 --> 00:19:14,000
and in this situation,
when the gate voltage drops

247
00:19:14,000 --> 00:19:17,000
below the source voltage,
this guy turns on.

248
00:19:17,000 --> 00:19:20,000
OK, so when there's a rising
guy that turns on in this

249
00:19:20,000 --> 00:19:24,000
particular situation when it
falls, the gate turns on and

250
00:19:24,000 --> 00:19:26,000
shows some resistance.
In this case,

251
00:19:26,000 --> 00:19:29,000
the resistance would be RON.
And to show that it's N

252
00:19:29,000 --> 00:19:34,000
channel, let me say N.
And in this case,

253
00:19:34,000 --> 00:19:39,000
the resistance,
when it turns on,

254
00:19:39,000 --> 00:19:44,000
would be RONp to represent P
channel.

255
00:19:44,000 --> 00:19:51,000
OK, so now consider the
following circuit for the

256
00:19:51,000 --> 00:19:56,000
inverter.
So, instead of my resistor,

257
00:19:56,000 --> 00:20:05,000
I put a complementary device,
OK, and that's it.

258
00:20:05,000 --> 00:20:09,000
So all I've done here is
replace my resistor with a

259
00:20:09,000 --> 00:20:14,000
MOSFET that behaves
complementary to the N channel

260
00:20:14,000 --> 00:20:16,000
MOSFET.
So this is my gate,

261
00:20:16,000 --> 00:20:19,000
my drain.
This is my source,

262
00:20:19,000 --> 00:20:22,000
my gate, my source,
and my drain.

263
00:20:22,000 --> 00:20:27,000
OK, and this guy is called a
pull up, and this guy is called

264
00:20:27,000 --> 00:20:33,000
a pull down.
OK, and the reason is that this

265
00:20:33,000 --> 00:20:37,000
guy pulls the output to ground
when it's turned on,

266
00:20:37,000 --> 00:20:41,000
while this guy,
when switched on,

267
00:20:41,000 --> 00:20:46,000
will pull this node up to VS.
So, I pull it down or pull it

268
00:20:46,000 --> 00:20:50,000
up based on when the VIN is high
or low.

269
00:20:50,000 --> 00:20:54,000
So, let's look at the two
situations.

270
00:20:54,000 --> 00:20:57,000
So, let's say,
as an example,

271
00:20:57,000 --> 00:21:00,000
my VS is 5V,
and let's say VIN in one

272
00:21:00,000 --> 00:21:05,000
situation being 5V,
and another situation being

273
00:21:05,000 --> 00:21:11,000
equal to 0V.
Let's draw the equivalent

274
00:21:11,000 --> 00:21:17,000
circuit in both these cases.
So, when VIN is high,

275
00:21:17,000 --> 00:21:22,000
I have my usual circuit.
When VIN is high,

276
00:21:22,000 --> 00:21:27,000
this MOSFET,
as before, when VIN is 5V,

277
00:21:27,000 --> 00:21:35,000
the N channel MOSFET below is
turned on, and so I have an RON

278
00:21:35,000 --> 00:21:40,000
resistance here.
But remember,

279
00:21:40,000 --> 00:21:45,000
VIN is 5, and VS is 5V,
then the voltage across the

280
00:21:45,000 --> 00:21:51,000
source and the gate of this P
channel FET is now equal,

281
00:21:51,000 --> 00:21:55,000
five and five.
OK, so this one would turn off.

282
00:21:55,000 --> 00:22:00,000
And that's the circuit that I
get.

283
00:22:00,000 --> 00:22:05,000
The output is suitably low.
In this situation,

284
00:22:05,000 --> 00:22:10,000
if VIN is zero,
what happens in this situation?

285
00:22:10,000 --> 00:22:13,000
Here's my output.
If VIN is 0V,

286
00:22:13,000 --> 00:22:17,000
the lower device turns off.
This is zero.

287
00:22:17,000 --> 00:22:21,000
This is zero.
This guy turns off,

288
00:22:21,000 --> 00:22:26,000
and that's the situation for
the N channel MOSFET.

289
00:22:26,000 --> 00:22:33,000
How about this guy here?
What happens here?

290
00:22:33,000 --> 00:22:37,000
This is at 5.
So let me just,

291
00:22:37,000 --> 00:22:41,000
this is at 5V.
OK, and VIN is at 0V.

292
00:22:41,000 --> 00:22:47,000
OK, so therefore,
the GS of this is -5V.

293
00:22:47,000 --> 00:22:52,000
If this is zero and this is
five, G, source,

294
00:22:52,000 --> 00:22:59,000
and drain, GS is -5V,
and -5V is significantly less

295
00:22:59,000 --> 00:23:06,000
than the threshold -1V in our
example.

296
00:23:06,000 --> 00:23:12,000
So, this one will switch on.
And if this one switches on,

297
00:23:12,000 --> 00:23:17,000
what I end up getting is RONp
out there.

298
00:23:17,000 --> 00:23:24,000
So, when this one kicks in,
it pulls the output high and VO

299
00:23:24,000 --> 00:23:28,000
goes high.
So, all I've done is replaced

300
00:23:28,000 --> 00:23:36,000
my resistor with a complementary
device, which switches off when

301
00:23:36,000 --> 00:23:41,000
the input is high,
and switches on when the input

302
00:23:41,000 --> 00:23:46,000
is low.
And the beauty of this is that

303
00:23:46,000 --> 00:23:50,000
at no point, assuming all the
devices are ideal here,

304
00:23:50,000 --> 00:23:55,000
at no point do I have a short
circuit between the output,

305
00:23:55,000 --> 00:23:59,000
do I have a current path from
the output to the ground from

306
00:23:59,000 --> 00:24:03,000
the supply to ground,
OK, I have this turned off or

307
00:24:03,000 --> 00:24:09,000
this turned off.
So, this type of logic

308
00:24:09,000 --> 00:24:18,000
involving a PMOS transistor
here, and the N channel

309
00:24:18,000 --> 00:24:25,000
transistor here is called CMOS
logic for, OK,

310
00:24:25,000 --> 00:24:31,000
it's called complementary MOS
logic.

311
00:24:31,000 --> 00:24:39,000
That's what CMOS comes from.
OK, so I'm sure you've read in

312
00:24:39,000 --> 00:24:43,000
a number of places that most
digital chips today use CMOS

313
00:24:43,000 --> 00:24:46,000
technology.
It comes from complementary

314
00:24:46,000 --> 00:24:51,000
MOS, and complementary comes
from the use of complementary

315
00:24:51,000 --> 00:24:55,000
transistors: N channel,
P channel, turns on when high,

316
00:24:55,000 --> 00:24:58,000
turns off when high,
turns off when low,

317
00:24:58,000 --> 00:25:01,000
turns on when low.
OK, that's exactly

318
00:25:01,000 --> 00:25:07,000
complementary to each other.
OK, so what you've seen here

319
00:25:07,000 --> 00:25:13,000
has been the workhorse of the
digital industry for the past

320
00:25:13,000 --> 00:25:16,000
two decades, 20 years,
CMOS logic.

321
00:25:16,000 --> 00:25:21,000
OK, and even the most advanced
chip from Intel has an inverter

322
00:25:21,000 --> 00:25:26,000
that looks exactly like that.
OK, if you count all the

323
00:25:26,000 --> 00:25:32,000
inverters in the universe today,
I would say a significant

324
00:25:32,000 --> 00:25:37,000
fraction of those look exactly
like that, no difference,

325
00:25:37,000 --> 00:25:42,000
just so simple.
So, the key with something like

326
00:25:42,000 --> 00:25:47,000
that is there is no path from
the power supply to the ground,

327
00:25:47,000 --> 00:25:51,000
and so by that model,
I did not consume any standby

328
00:25:51,000 --> 00:25:54,000
power.
OK, my standby power in that

329
00:25:54,000 --> 00:25:58,000
idealized model is zero.
So, let's compute P.

330
00:25:58,000 --> 00:26:04,000
So, what is P dynamic?
Let's use the method that we

331
00:26:04,000 --> 00:26:11,000
adopted in the last lecture,
and draw the equivalent

332
00:26:11,000 --> 00:26:18,000
circuit, and compute the power.
OK, so I'm going to model the

333
00:26:18,000 --> 00:26:24,000
following situation,
and assume that I drive a

334
00:26:24,000 --> 00:26:26,000
capacitive load,
C.

335
00:26:26,000 --> 00:26:32,000
OK, and as an input,
as I did the last time,

336
00:26:32,000 --> 00:26:38,000
I'm going to assume I have some
input voltage,

337
00:26:38,000 --> 00:26:45,000
VIN, that looks like this.
The cycle time,

338
00:26:45,000 --> 00:26:53,000
T, and the frequency is 1/t,
and let me assume that this is

339
00:26:53,000 --> 00:26:59,000
T1, and this is T2.
OK, and I'm assuming that T1

340
00:26:59,000 --> 00:27:09,000
and T2 are both much larger than
the respective time constants.

341
00:27:09,000 --> 00:27:13,000
OK, the time constants when,
for discharging here,

342
00:27:13,000 --> 00:27:18,000
is C RONn, and here the
relevant resistance is RONp.

343
00:27:18,000 --> 00:27:23,000
The charging time constant is
RONp times C.

344
00:27:23,000 --> 00:27:30,000
OK, so T1 and T2 are assumed to
be much greater than these two.

345
00:27:30,000 --> 00:27:34,000
So when you look at this,
there's one other benefit

346
00:27:34,000 --> 00:27:38,000
besides the power benefit,
OK, of using CMOS logic

347
00:27:38,000 --> 00:27:43,000
compared to using NMOS.
OK, it not only cuts out my

348
00:27:43,000 --> 00:27:46,000
standby power,
but there is another

349
00:27:46,000 --> 00:27:51,000
significant advantage which is
almost equal to the power

350
00:27:51,000 --> 00:27:54,000
advantage of this kind of CMOS
technology.

351
00:27:54,000 --> 00:28:00,000
Anybody have any ideas?
What's the advantage?

352
00:28:00,000 --> 00:28:05,000
What does intuition tell you?
Is CMOS going to be faster or

353
00:28:05,000 --> 00:28:07,000
slower than NMOS?
Why?

354
00:28:07,000 --> 00:28:11,000
That's right.
The key here is that the NMOS

355
00:28:11,000 --> 00:28:16,000
design I showed you earlier was
relatively slow because it took

356
00:28:16,000 --> 00:28:21,000
me a while to charge up the load
capacitor from RL.

357
00:28:21,000 --> 00:28:24,000
In this situation,
RL will become really,

358
00:28:24,000 --> 00:28:27,000
really small;
it's RONp.

359
00:28:27,000 --> 00:28:32,000
It's roughly the same magnitude
as RONm.

360
00:28:32,000 --> 00:28:35,000
OK, if so both of these on
resistances are more or less

361
00:28:35,000 --> 00:28:39,000
equal and small,
then the rise time will be of

362
00:28:39,000 --> 00:28:42,000
the same order of magnitude as
the fall time,

363
00:28:42,000 --> 00:28:45,000
which makes this much faster
than the NMOS.

364
00:28:45,000 --> 00:28:49,000
In NMOS, my time constant was
RLC, and RL was pretty large.

365
00:28:49,000 --> 00:28:53,000
In this case it's RONp C,
and RONp can be made to be very

366
00:28:53,000 --> 00:28:58,000
small because when it's switched
off, the resistance here is

367
00:28:58,000 --> 00:29:02,000
infinity.
So, in this situation,

368
00:29:02,000 --> 00:29:07,000
if I assume T1 and T2 are much
larger than the respective time

369
00:29:07,000 --> 00:29:12,000
constants, I can go ahead and
draw my equivalent circuit.

370
00:29:12,000 --> 00:29:16,000
So, here's VS.
So, for charging up,

371
00:29:16,000 --> 00:29:20,000
let's say this one is going to
a one, or to a high.

372
00:29:20,000 --> 00:29:24,000
So, I have VS going through a
resistor, RONp,

373
00:29:24,000 --> 00:29:30,000
to a capacitor,
and this thing is a switch.

374
00:29:30,000 --> 00:29:34,000
So I have RONp,
an ideal switch,

375
00:29:34,000 --> 00:29:40,000
going to a capacitor,
C, this is my V out node,

376
00:29:40,000 --> 00:29:46,000
OK, so it's VS going through a
resistance, RONp,

377
00:29:46,000 --> 00:29:50,000
an ideal switch,
to a capacitor,

378
00:29:50,000 --> 00:29:54,000
C.
That's a charging circuit.

379
00:29:54,000 --> 00:30:00,000
For discharging,
I have C, discharging through

380
00:30:00,000 --> 00:30:06,000
an ideal switch with RONn.
So, this situation,

381
00:30:06,000 --> 00:30:12,000
I have an ideal switch,
RONn.

382
00:30:12,000 --> 00:30:20,000
OK, so that's the equivalent
circuit for something like this.

383
00:30:20,000 --> 00:30:27,000
So, in this circuit,
during T1, this guy's off,

384
00:30:27,000 --> 00:30:31,000
and this guy's on,
on during T1,

385
00:30:31,000 --> 00:30:37,000
and off otherwise.
This guy is on during T2,

386
00:30:37,000 --> 00:30:41,000
and off otherwise.
OK, so just imagine,

387
00:30:41,000 --> 00:30:45,000
this guy switches on,
this guy switches off,

388
00:30:45,000 --> 00:30:49,000
this guy switches on,
this guy switches off,

389
00:30:49,000 --> 00:30:50,000
OK?
And remember,

390
00:30:50,000 --> 00:30:56,000
this is exactly the circuit I
had analyzed last time in the

391
00:30:56,000 --> 00:30:59,000
last lecture,
and the result given by v

392
00:30:59,000 --> 00:31:03,000
double asterisk.
And that result was simply

393
00:31:03,000 --> 00:31:10,000
average power being CVS^2f.
That's the exact circuit we

394
00:31:10,000 --> 00:31:13,000
used to compute the dynamic
power, CVS^2f.

395
00:31:13,000 --> 00:31:17,000
OK, so we're done.
And how did this come about?

396
00:31:17,000 --> 00:31:21,000
This came about because the
intuition here is that I'm

397
00:31:21,000 --> 00:31:26,000
charging up the capacitor fully,
and then I'm discharging the

398
00:31:26,000 --> 00:31:30,000
capacitor through this other
side, OK, and I'm consuming

399
00:31:30,000 --> 00:31:35,000
power, dissipating power,
in these two resistances during

400
00:31:35,000 --> 00:31:39,000
charge up and during the
discharge.

401
00:31:39,000 --> 00:31:43,000
Half the power gets consumed
during charge up,

402
00:31:43,000 --> 00:31:49,000
and half during the discharge.
So, I'd like to go back to

403
00:31:49,000 --> 00:31:54,000
doing a few numbers here,
and taking a look at how,

404
00:31:54,000 --> 00:31:59,000
even with this expression,
life can get pretty thorny as

405
00:31:59,000 --> 00:32:04,000
we go ahead into the next
decade.

406
00:32:04,000 --> 00:32:15,000
OK, so for our previous
example, we assumed that 10^8

407
00:32:15,000 --> 00:32:22,000
gates, F=1 GHz,
C=0.1 femtofarads,

408
00:32:22,000 --> 00:32:32,000
VS was 5V, and I don't need RL
anymore.

409
00:32:32,000 --> 00:32:36,000
OK, why is it that I don't have
any resistance component here?

410
00:32:36,000 --> 00:32:40,000
I don't have it here because
the power consumed by this

411
00:32:40,000 --> 00:32:44,000
circuit is independent of those
resistances, provided T1 and T2

412
00:32:44,000 --> 00:32:48,000
are long enough,
are much longer than the two

413
00:32:48,000 --> 00:32:50,000
time constants,
RONp C, and RONn C.

414
00:32:50,000 --> 00:32:53,000
OK, so I don't have RL in my
equation anymore.

415
00:32:53,000 --> 00:33:00,000
I don't have any standby power.
So, based on this calculation,

416
00:33:00,000 --> 00:33:08,000
the calculation I did up there
showed that I had 2.5 microwatts

417
00:33:08,000 --> 00:33:16,000
per gate, and for 10^8 gates I
had 250W for a chip with 10^8

418
00:33:16,000 --> 00:33:21,000
gates.
So, I'd like to dwell on this,

419
00:33:21,000 --> 00:33:27,000
if you can move over to page
eight in your notes,

420
00:33:27,000 --> 00:33:31,000
here.
Let me dwell on this for some

421
00:33:31,000 --> 00:33:38,000
time, and pontificate on a few
things.

422
00:33:38,000 --> 00:33:40,000
First of all,
this number,

423
00:33:40,000 --> 00:33:43,000
as I said before,
is high, but not a disaster.

424
00:33:43,000 --> 00:33:48,000
OK, so you can't use this in
laptops, but it's quite OK for a

425
00:33:48,000 --> 00:33:51,000
desktop or a server,
and so on.

426
00:33:51,000 --> 00:33:55,000
If you just go and put your ear
to a pedestal computer,

427
00:33:55,000 --> 00:34:00,000
you'll always hear it making a
sound, and that sound is because

428
00:34:00,000 --> 00:34:07,000
of a big fan that's inside it.
And, if you have a big enough

429
00:34:07,000 --> 00:34:10,000
fan, 250W is not such a big
deal.

430
00:34:10,000 --> 00:34:17,000
But, this is certainly a real
problem for mobile devices.

431
00:34:17,000 --> 00:34:20,000
For a laptop,
this is unthinkable.

432
00:34:20,000 --> 00:34:24,000
OK, so we have to deal with
this.

433
00:34:24,000 --> 00:34:30,000
The second issue is the
following, that it's 250W for

434
00:34:30,000 --> 00:34:34,000
1GHz.
Now, the fastest Pentium 4s

435
00:34:34,000 --> 00:34:39,000
that money can by today are,
what, how many GHz?

436
00:34:39,000 --> 00:34:44,000
What's the fastest Pentium 4
you can buy today?

437
00:34:44,000 --> 00:34:47,000
What's that?
Does anybody have a 4GHz

438
00:34:47,000 --> 00:34:51,000
Pentium 4 here?
Oh, darn, you beat me.

439
00:34:51,000 --> 00:34:53,000
Anybody have a 3?
3GHz?

440
00:34:53,000 --> 00:34:57,000
A couple.
So, I have a couple of 3GHz

441
00:34:57,000 --> 00:35:03,000
machines, and our lab has a
whole ton of them.

442
00:35:03,000 --> 00:35:06,000
So, if Intel comes out with
4GHz machines today,

443
00:35:06,000 --> 00:35:11,000
they've been going up by about
1GHz roughly every year for the

444
00:35:11,000 --> 00:35:14,000
past couple of years.
And, within three or four

445
00:35:14,000 --> 00:35:19,000
years, you're going to see
chips, microprocessors that are

446
00:35:19,000 --> 00:35:22,000
in the 5-10GHz range,
OK, assuming that all other

447
00:35:22,000 --> 00:35:26,000
things stay equal,
which of course they're not,

448
00:35:26,000 --> 00:35:29,000
but just to give you some
insight here,

449
00:35:29,000 --> 00:35:33,000
if I clock these guys and build
circuits that are ten times

450
00:35:33,000 --> 00:35:37,000
faster, I very soon go up to
2.5kW, again as I said,

451
00:35:37,000 --> 00:35:42,000
all things being equal which
they're not.

452
00:35:42,000 --> 00:35:46,000
But just to give you a sense,
as I increase my frequency,

453
00:35:46,000 --> 00:35:49,000
so does the power consumed by
the chip, OK?

454
00:35:49,000 --> 00:35:52,000
So, I really have to do
something here.

455
00:35:52,000 --> 00:35:55,000
So, if I stare at this
equation, CVS^2f,

456
00:35:55,000 --> 00:35:59,000
I want to increase f because
people will buy computers if I

457
00:35:59,000 --> 00:36:03,000
have higher frequencies.
And, Intel has managed to use

458
00:36:03,000 --> 00:36:07,000
its marketing campaigns to
pretty much convince consumers

459
00:36:07,000 --> 00:36:12,000
that high frequencies are a good
thing.

460
00:36:12,000 --> 00:36:15,000
OK, and whether they really
mean anything or not,

461
00:36:15,000 --> 00:36:19,000
that's a different issue.
So, we've got this huge power

462
00:36:19,000 --> 00:36:22,000
for assuming 5V,
OK, so it turns out that

463
00:36:22,000 --> 00:36:25,000
microprocessors,
as they come out,

464
00:36:25,000 --> 00:36:29,000
newer and newer versions run at
lower and lower voltages.

465
00:36:29,000 --> 00:36:33,000
OK, they invent technologies
that use lower and lower

466
00:36:33,000 --> 00:36:38,000
voltages, and go from VS 5V to,
today, VS on the order of 1.5

467
00:36:38,000 --> 00:36:44,000
to 1V, somewhere in that range.
So the moment you do that,

468
00:36:44,000 --> 00:36:47,000
you get a 25x reduction in
power.

469
00:36:47,000 --> 00:36:51,000
OK, so in going from 2.5kW,
you would now come down to

470
00:36:51,000 --> 00:36:56,000
something on the order of 100W,
which is, again,

471
00:36:56,000 --> 00:37:00,000
much more reasonable,
again, all other things being

472
00:37:00,000 --> 00:37:03,000
equal.
It turns out that the

473
00:37:03,000 --> 00:37:07,000
capacitance of devices also
changes as you go to smaller and

474
00:37:07,000 --> 00:37:10,000
smaller devices.
And, 100W is also pretty high,

475
00:37:10,000 --> 00:37:13,000
and still not good enough for
mobile computers.

476
00:37:13,000 --> 00:37:16,000
So, there are many,
many other tricks that people

477
00:37:16,000 --> 00:37:20,000
use to get even lower powers.
One trick is to play games with

478
00:37:20,000 --> 00:37:22,000
the clock.
OK, what you do is,

479
00:37:22,000 --> 00:37:26,000
let's say for example in some
computation you are not going to

480
00:37:26,000 --> 00:37:30,000
be using your floating point
unit.

481
00:37:30,000 --> 00:37:33,000
Or let's say I'm going to be
using your integer adder unit.

482
00:37:33,000 --> 00:37:37,000
OK, so what you can do is you
can turn off the clock to those

483
00:37:37,000 --> 00:37:41,000
devices so that those devices do
not even switch when they're not

484
00:37:41,000 --> 00:37:43,000
working.
OK, if I turn off the clock to

485
00:37:43,000 --> 00:37:46,000
a device, the device isn't even
going to switch,

486
00:37:46,000 --> 00:37:50,000
it's just going to sit there in
limbo without consuming any

487
00:37:50,000 --> 00:37:52,000
power.
It's equivalent to turning off

488
00:37:52,000 --> 00:37:55,000
both transistors.
If you turn off both the PMOS

489
00:37:55,000 --> 00:37:58,000
and NMOS somehow,
OK, it's not consuming any

490
00:37:58,000 --> 00:38:01,000
power.
And by doing that,

491
00:38:01,000 --> 00:38:03,000
you can further cut down the
power.

492
00:38:03,000 --> 00:38:06,000
So, if you can idle some of
your function units,

493
00:38:06,000 --> 00:38:10,000
it's called idling a function
unit, idle a function unit for,

494
00:38:10,000 --> 00:38:14,000
let's say, half the time.
OK, you would cut down power by

495
00:38:14,000 --> 00:38:17,000
another factor of two.
We can idle,

496
00:38:17,000 --> 00:38:19,000
then, 75% of the time,
come down to 25W.

497
00:38:19,000 --> 00:38:23,000
So, those are the classes of
tricks that people play.

498
00:38:23,000 --> 00:38:26,000
I'm going to stop here and
allow the underground guide

499
00:38:26,000 --> 00:38:30,000
folks to do the survey.
But, suffice it to say that the

500
00:38:30,000 --> 00:38:34,000
power discussion that I've gone
through with you is a very high

501
00:38:34,000 --> 00:38:39,000
level discussion as to the real
thing.

502
00:38:39,000 --> 00:38:41,000
In real life,
what actually happens is that

503
00:38:41,000 --> 00:38:44,000
there is a fair amount of
standby power even for CMOS

504
00:38:44,000 --> 00:38:46,000
logic.
It turns out that although I

505
00:38:46,000 --> 00:38:50,000
don't have a path from VS to
ground for my two transistors,

506
00:38:50,000 --> 00:38:53,000
it turns out that there are
many leakage currents.

507
00:38:53,000 --> 00:38:57,000
OK, currents leak through all
kinds of places through the

508
00:38:57,000 --> 00:38:59,000
drain of the inverter,
and so on and so forth.

509
00:38:59,000 --> 00:39:03,000
And so, there is some standby
power.

510
00:39:03,000 --> 00:39:06,000
So, let me show you a quick
demo while, I guess,

511
00:39:06,000 --> 00:39:09,000
the review handouts are going
around.

512
00:39:09,000 --> 00:39:13,000
And this shows the temperature
of my CMOS inverter,

513
00:39:13,000 --> 00:39:17,000
and as I increase the
frequency, you can just watch

514
00:39:17,000 --> 00:39:21,000
the temperature go up,
and hopefully we'll blow this

515
00:39:21,000 --> 00:39:24,000
transistor.
So, I'm increasing the

516
00:39:24,000 --> 00:39:29,000
frequency as you can see on the
side here, and higher frequency

517
00:39:29,000 --> 00:39:33,000
implies more power consumption,
more temperature,

518
00:39:33,000 --> 00:39:37,000
OK, and hopefully you will see
some smoke coming out of,

519
00:39:37,000 --> 00:39:42,000
OK, I think I blew the
inverter.

520
00:39:42,000 --> 00:39:46,000
So, the output is gone.
So, it's at 110 degrees there,

521
00:39:46,000 --> 00:39:49,000
and that blew it.
Sometimes we see smoke come

522
00:39:49,000 --> 00:39:54,000
out, but I guess today is not
one of our lucky days.

523
00:39:54,000 --> 00:39:58,000
OK, so let me stop here and
have the underground guide folks

524
00:39:58,000 --> 00:40:01,000
go through the reviews.