1 00:00:00,500 --> 00:00:02,330 PROFESSOR: Propositional operators 2 00:00:02,330 --> 00:00:04,790 play a basic role in the design of digital circuitry, 3 00:00:04,790 --> 00:00:07,230 and we're going to illustrate that in the section 4 00:00:07,230 --> 00:00:11,130 by designing a little binary addition circuit. 5 00:00:11,130 --> 00:00:15,850 So let's begin with a review of binary notation and addition 6 00:00:15,850 --> 00:00:16,730 in binary. 7 00:00:16,730 --> 00:00:20,590 So the way binary works is like decimal. 8 00:00:20,590 --> 00:00:22,200 Except instead of using powers of 10, 9 00:00:22,200 --> 00:00:23,650 you're using powers of 2. 10 00:00:23,650 --> 00:00:26,510 So here is the binary representation of the number 11 00:00:26,510 --> 00:00:27,800 39. 12 00:00:27,800 --> 00:00:30,170 The way to understand that is this is the ones place. 13 00:00:30,170 --> 00:00:31,340 That's the twos place. 14 00:00:31,340 --> 00:00:33,460 That's the fours place. 15 00:00:33,460 --> 00:00:39,140 So 1 plus 2 plus 4 is 7. 16 00:00:39,140 --> 00:00:41,120 Then this is the eighth place with nothing, 17 00:00:41,120 --> 00:00:42,980 this is the 16th place with something, 18 00:00:42,980 --> 00:00:45,370 and this is the 32 place with 1. 19 00:00:45,370 --> 00:00:49,200 So we get 32 to 7, and get 39. 20 00:00:49,200 --> 00:00:55,170 Likewise, the binary representation of 28 is 011100. 21 00:00:55,170 --> 00:01:00,104 I'll let you check how that works with contributing 1, 2, 22 00:01:00,104 --> 00:01:03,430 4, 8, 16, and 32. 23 00:01:03,430 --> 00:01:06,580 And finally, let's add these two numbers in binary. 24 00:01:06,580 --> 00:01:09,590 Now, binary addition works just like decimal addition 25 00:01:09,590 --> 00:01:12,400 except that the only numbers are ones and zeros 26 00:01:12,400 --> 00:01:16,390 so that when you get 1 plus 1, you have to carry 1. 27 00:01:16,390 --> 00:01:17,220 Let's do that. 28 00:01:17,220 --> 00:01:19,369 So 1 plus 0 is 1. 29 00:01:19,369 --> 00:01:20,660 That fills in the first column. 30 00:01:20,660 --> 00:01:23,690 Now we have another 1 plus 0 is 1. 31 00:01:23,690 --> 00:01:24,690 That's fine. 32 00:01:24,690 --> 00:01:26,810 Now we have a 1 plus 1. 33 00:01:26,810 --> 00:01:31,000 And that's going do a 0 here and contribute a carry of 1 34 00:01:31,000 --> 00:01:32,610 to the next column. 35 00:01:32,610 --> 00:01:34,890 Now, the next column has two ones. 36 00:01:34,890 --> 00:01:37,890 So it becomes a 0 and contributes 37 00:01:37,890 --> 00:01:38,730 to another carrying. 38 00:01:38,730 --> 00:01:40,200 Now we have two ones. 39 00:01:40,200 --> 00:01:42,250 We get a 0 and contribute another carry. 40 00:01:42,250 --> 00:01:46,480 And now we have two ones, and we finally get a 1 0. 41 00:01:46,480 --> 00:01:49,255 So this is the binary representation of the sum, 42 00:01:49,255 --> 00:01:54,840 and you can check that this is 1 plus 2 is 3 plus 64. 43 00:01:54,840 --> 00:01:57,310 So the answer should be 67. 44 00:01:57,310 --> 00:01:59,050 And you can check that it is. 45 00:01:59,050 --> 00:02:00,610 So that's how binary addition works. 46 00:02:00,610 --> 00:02:05,170 So now let's try to design a bit of circuitry using 47 00:02:05,170 --> 00:02:11,400 digital logic signals of 0 and 1, which will do addition. 48 00:02:11,400 --> 00:02:16,280 And so we're going to try to design a little six bit 49 00:02:16,280 --> 00:02:17,335 binary addition circuit. 50 00:02:17,335 --> 00:02:19,890 So I'm going to have as inputs, the six 51 00:02:19,890 --> 00:02:24,960 digits of the first binary number-- a 5 down through a 0 52 00:02:24,960 --> 00:02:26,890 and then the second binary number. 53 00:02:26,890 --> 00:02:28,690 Let's call it b 0 through b 5. 54 00:02:28,690 --> 00:02:32,580 So these are two binary numbers that are six digits long, 55 00:02:32,580 --> 00:02:37,330 and I'm going to add them up by thinking of a 1 as a 0 or 1 56 00:02:37,330 --> 00:02:41,320 signal. a 0 is a 0 1 signal. b 0 is a 0 1 signal. 57 00:02:41,320 --> 00:02:44,060 And these can be transmitted down wires 58 00:02:44,060 --> 00:02:48,830 into some boxes that contain digital operators that 59 00:02:48,830 --> 00:02:51,030 will cause the right signals to come out. 60 00:02:51,030 --> 00:02:53,080 And what we want to come out of here 61 00:02:53,080 --> 00:02:58,060 is the possibly seven digit representation 62 00:02:58,060 --> 00:03:01,140 of their binary sum. 63 00:03:01,140 --> 00:03:06,980 So d 0 is the sum of a 0 and b 0-- the lower digit possibly 64 00:03:06,980 --> 00:03:08,810 with carry and so on. 65 00:03:08,810 --> 00:03:14,210 And then c 5 if the sum of two six digit numbers 66 00:03:14,210 --> 00:03:15,880 runs to seven digits, which it might 67 00:03:15,880 --> 00:03:17,850 as we saw in the previous example, 68 00:03:17,850 --> 00:03:20,910 then c 5 would become 1, otherwise 0. 69 00:03:20,910 --> 00:03:22,790 So this is the specification. 70 00:03:22,790 --> 00:03:26,810 I want a and b to come in, and I want their binary sum 71 00:03:26,810 --> 00:03:30,930 to come out as d's with a high order c if need be. 72 00:03:32,440 --> 00:03:34,360 Now, the way I'm going to do that is 73 00:03:34,360 --> 00:03:38,550 it's clear that the behavior of the inputs for a and b, 74 00:03:38,550 --> 00:03:42,600 which produced the lower digit, might produce a carry, 75 00:03:42,600 --> 00:03:45,310 and that carry has to be transmitted to the next column 76 00:03:45,310 --> 00:03:46,570 if it exists. 77 00:03:46,570 --> 00:03:49,130 So I'm going to need a wire that sends a 0 1 78 00:03:49,130 --> 00:03:54,960 signal from this box over to that one that carries 0 or 1 79 00:03:54,960 --> 00:03:56,900 and likewise for all of the others. 80 00:03:56,900 --> 00:04:01,450 So this is the kind of basic structure of my binary addition 81 00:04:01,450 --> 00:04:01,950 circuit. 82 00:04:01,950 --> 00:04:04,720 This is called a ripple carry organization. 83 00:04:04,720 --> 00:04:10,170 It's mimicking exactly the way that we added up to two numbers 84 00:04:10,170 --> 00:04:15,670 column by column, possibly propagating carry of 0 or 1-- 85 00:04:15,670 --> 00:04:18,390 or really a carry of just 1 to the next column. 86 00:04:18,390 --> 00:04:20,750 And I've got all the wires in place that I need. 87 00:04:20,750 --> 00:04:23,300 What we need to do is design the digital circuitry 88 00:04:23,300 --> 00:04:24,929 that's in those boxes. 89 00:04:24,929 --> 00:04:26,720 Well, this box is different from the others 90 00:04:26,720 --> 00:04:28,070 because it's only got two inputs. 91 00:04:28,070 --> 00:04:29,444 All the others have three inputs. 92 00:04:29,444 --> 00:04:33,410 So the three input boxes, we'll call full adders and the two 93 00:04:33,410 --> 00:04:35,380 input boxes a half an adder. 94 00:04:35,380 --> 00:04:37,300 And the specification of a half an adder, 95 00:04:37,300 --> 00:04:44,250 again, is that the output is the binary representation of a 0 96 00:04:44,250 --> 00:04:45,130 plus b 0. 97 00:04:45,130 --> 00:04:47,740 So it's a two digit binary representation-- never 98 00:04:47,740 --> 00:04:51,120 be bigger than 2 because there's only two numbers. 99 00:04:51,120 --> 00:04:55,120 The output of a full adder is it gets three inputs 100 00:04:55,120 --> 00:04:56,560 in this case-- b 1, a 1. 101 00:04:56,560 --> 00:04:58,750 And the carry, c 0. 102 00:04:58,750 --> 00:05:02,880 And it produces the binary representation 103 00:05:02,880 --> 00:05:04,900 of the sum of those three numbers, which 104 00:05:04,900 --> 00:05:08,120 is a two digit binary representation that 105 00:05:08,120 --> 00:05:12,160 might be anything from 0 to 3. 106 00:05:12,160 --> 00:05:12,839 OK. 107 00:05:12,839 --> 00:05:14,380 Well, let's start with the easy case. 108 00:05:14,380 --> 00:05:15,280 What's a half adder? 109 00:05:15,280 --> 00:05:18,140 Well, a half adder, again, has inputs b and a, 110 00:05:18,140 --> 00:05:20,170 and it's supposed to produce as output 111 00:05:20,170 --> 00:05:22,200 the binary representation of b plus a. 112 00:05:22,200 --> 00:05:26,960 So d is the lower digit in the zeros place, 113 00:05:26,960 --> 00:05:30,530 and c is the high order digit, namely the twos place. 114 00:05:30,530 --> 00:05:31,860 Well, what does that look like? 115 00:05:31,860 --> 00:05:32,901 Well, here's the circuit. 116 00:05:32,901 --> 00:05:34,920 This is the digital designer symbol 117 00:05:34,920 --> 00:05:38,110 for an exclusive [INAUDIBLE] gate that returns. 118 00:05:38,110 --> 00:05:42,240 So d is going to be the exclusive or of a and b 119 00:05:42,240 --> 00:05:45,460 according to this pictorial diagram. 120 00:05:45,460 --> 00:05:47,220 Notice I'm using this colon colon 121 00:05:47,220 --> 00:05:51,980 equal symbol which is convenient as a reminder 122 00:05:51,980 --> 00:05:54,200 that I'm defining the thing on the left. 123 00:05:54,200 --> 00:05:56,170 You could replace it by equal, but it's 124 00:05:56,170 --> 00:05:59,150 informative to realize that it's not an equality that you've 125 00:05:59,150 --> 00:06:02,320 proved or that some derivation of the two interesting things 126 00:06:02,320 --> 00:06:04,480 are proven to be equal, but rather that I'm just 127 00:06:04,480 --> 00:06:06,670 defining what the d is. 128 00:06:06,670 --> 00:06:10,620 This output d is defined to be a XOR b. 129 00:06:10,620 --> 00:06:12,780 And likewise, this is an AND gate. 130 00:06:12,780 --> 00:06:15,866 So the output c a AND b. 131 00:06:15,866 --> 00:06:16,740 And let's check that. 132 00:06:16,740 --> 00:06:19,540 The low order digit is definitely the [INAUDIBLE] sum, 133 00:06:19,540 --> 00:06:21,320 XOR of a and b. 134 00:06:21,320 --> 00:06:23,124 And when is there a carry? 135 00:06:23,124 --> 00:06:24,540 Well, the only way there's a carry 136 00:06:24,540 --> 00:06:28,720 is when the value is 2, in which case the output c would be 1 137 00:06:28,720 --> 00:06:29,940 and d would be 0. 138 00:06:29,940 --> 00:06:32,330 And that's exactly when both a and b 139 00:06:32,330 --> 00:06:34,780 are 1, that is c is a and b. 140 00:06:34,780 --> 00:06:35,790 So that's a half adder. 141 00:06:35,790 --> 00:06:37,970 That was easy. 142 00:06:37,970 --> 00:06:40,060 Well, a full adder looks like this. 143 00:06:40,060 --> 00:06:41,520 It's a little bit more complicated, 144 00:06:41,520 --> 00:06:44,180 and I'm going to write out the equations without trying 145 00:06:44,180 --> 00:06:45,510 to justify them completely. 146 00:06:45,510 --> 00:06:48,960 But I need a name in order to describe this 147 00:06:48,960 --> 00:06:50,420 with propositional operators. 148 00:06:50,420 --> 00:06:52,110 I need a name for that important signal. 149 00:06:52,110 --> 00:06:56,789 Call it s, which is what we were not 150 00:06:56,789 --> 00:06:58,080 calling it in the previous one. 151 00:06:58,080 --> 00:07:00,310 But now this is a half adder with inputs a 152 00:07:00,310 --> 00:07:06,090 and b and outputs s, which is a XOR b and another output 153 00:07:06,090 --> 00:07:08,885 here, which we know is just going to be a and b. 154 00:07:08,885 --> 00:07:09,550 OK. 155 00:07:09,550 --> 00:07:12,640 How do I express this set of connections as formulas? 156 00:07:12,640 --> 00:07:15,840 Well, first of all, s is the output of this first half 157 00:07:15,840 --> 00:07:18,240 adder, which is a XOR b. 158 00:07:18,240 --> 00:07:20,950 OK. 159 00:07:20,950 --> 00:07:25,220 The output d I get by taking s, and it's 160 00:07:25,220 --> 00:07:27,660 the first output of the second half adder, which 161 00:07:27,660 --> 00:07:30,930 means it's c in XOR or s. 162 00:07:30,930 --> 00:07:32,070 That's easy. 163 00:07:32,070 --> 00:07:33,850 And what about c out? 164 00:07:33,850 --> 00:07:38,370 Well, c out is getting-- this is an OR gate by the way. 165 00:07:38,370 --> 00:07:41,110 So c out is going to be an OR of what comes out 166 00:07:41,110 --> 00:07:43,690 of this half adder, which is c in 167 00:07:43,690 --> 00:07:50,000 and c s and OR with the output of this half adder, which 168 00:07:50,000 --> 00:07:51,720 is just a and b. 169 00:07:51,720 --> 00:07:53,920 So there are a bunch of equations 170 00:07:53,920 --> 00:07:58,150 that completely characterize the structure of this little bit 171 00:07:58,150 --> 00:08:03,210 of digital logic and how it is wired up and fits together. 172 00:08:03,210 --> 00:08:07,440 Now, let's go back to describing our ripple carry circuit 173 00:08:07,440 --> 00:08:09,860 of what was going on here. 174 00:08:09,860 --> 00:08:12,900 Now that we have the equations that characterize the behavior 175 00:08:12,900 --> 00:08:14,810 of these full adders and half adders, 176 00:08:14,810 --> 00:08:18,400 I can explain to you what the formulas are for all of these 177 00:08:18,400 --> 00:08:20,825 outputs-- the c's and the d's. 178 00:08:20,825 --> 00:08:22,190 And that goes as follows. 179 00:08:22,190 --> 00:08:25,460 So the first one, looking at this half adder with a 0, b 0 180 00:08:25,460 --> 00:08:27,930 coming in and c 0, d 0 coming out, 181 00:08:27,930 --> 00:08:34,950 I know that d 0 is a 0 XOR b 0 and c 0 is a 0 AND b0. 182 00:08:34,950 --> 00:08:38,580 That's just that the formulas that we have for the half 183 00:08:38,580 --> 00:08:41,960 adder when the inputs are a 0 and b 0 and I call the outputs 184 00:08:41,960 --> 00:08:44,059 b 0 and c 0. 185 00:08:44,059 --> 00:08:47,460 Now, the more general case of the full adder-- 186 00:08:47,460 --> 00:08:50,950 what's coming in here is an a and a b 187 00:08:50,950 --> 00:08:53,320 with the same subscript-- a i and b i. 188 00:08:53,320 --> 00:08:58,380 And what's coming out is the ith digit of the binary sum, d i 189 00:08:58,380 --> 00:09:00,700 and the carry c i. 190 00:09:00,700 --> 00:09:04,420 And I could describe those just by using the formulas 191 00:09:04,420 --> 00:09:05,500 for the full adder. 192 00:09:05,500 --> 00:09:07,210 So what it means is that I'm going 193 00:09:07,210 --> 00:09:09,170 to introduce a new convening variable, 194 00:09:09,170 --> 00:09:13,952 s i, which I'm going to define to be a i or XOR b i. 195 00:09:13,952 --> 00:09:16,980 D i is then going to be c i minus 1-- the 196 00:09:16,980 --> 00:09:21,100 carry from the previous place-- XOR with s i. 197 00:09:21,100 --> 00:09:25,630 And the new carry, c i, is going to be 198 00:09:25,630 --> 00:09:30,780 the output of the first half adder, which is c i minus 1 199 00:09:30,780 --> 00:09:34,000 AND s i or the output of the first half adder, which 200 00:09:34,000 --> 00:09:35,480 is a i and b i. 201 00:09:35,480 --> 00:09:38,700 So the point is that I've just taken the wiring 202 00:09:38,700 --> 00:09:41,830 and translated it into equations like this, 203 00:09:41,830 --> 00:09:47,810 and you can see how these equations might be better 204 00:09:47,810 --> 00:09:51,130 to use than the particular way that you drew 205 00:09:51,130 --> 00:09:52,800 the picture with all the wires connected 206 00:09:52,800 --> 00:09:55,000 because the logical behavior of the circuit 207 00:09:55,000 --> 00:09:56,570 doesn't depend on how it's laid out. 208 00:09:56,570 --> 00:10:00,550 It just depends on these logical connectives between the values 209 00:10:00,550 --> 00:10:02,790 of these different variables.