Integrated circuit. (Image courtesy of Ernest Orlando Lawrence Berkeley National Laboratory.)
Instructor(s)
Prof. Anantha Chandrakasan
MIT Course Number
6.374
As Taught In
Fall 2003
Level
Graduate
Course Description
Course Features
Course Highlights
This course site features documentation on CAD tools used in 6.374, along with other materials used by students in the course.
Course Description
6.374 examines the device and circuit level optimization of digital building blocks. Topics covered include: MOS device models including Deep Sub-Micron effects; circuit design styles for logic, arithmetic and sequential blocks; estimation and minimization of energy consumption; interconnect models and parasitics; device sizing and logical effort; timing issues (clock skew and jitter) and active clock distribution techniques; memory architectures, circuits (sense amplifiers) and devices; testing of integrated circuits. The course employs extensive use of circuit layout and SPICE in design projects and software labs.